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    OUTPUT CIRCUIT
    3.
    发明申请
    OUTPUT CIRCUIT 审中-公开

    公开(公告)号：US20200042029A1

    公开(公告)日：2020-02-06

    申请号：US16600123

    申请日：2019-10-11

    Applicant: SOCIONEXT INC.

    Inventor： Kyota SHIMIZU ,  Toshiya SUZUKI ,  Tomohiko KOTO

    IPC: G05F1/618 ,  H03K19/00 ,  H03K19/0175 ,  H03K3/356 ,  H03K19/003 ,  G11C7/10 ,  H03K3/281

    Abstract: An output circuit includes: a first p-type transistor having a source connected to VDDH and a gate to which an input signal is fed; and a second p-type transistor having a source connected to the drain of the first p-type transistor, a drain connected to an output terminal, and a gate connected to a first node. A capacitor has one terminal to which the input signal is fed and the other terminal connected to the first node. A first n-type transistor has a source connected to VDDL, a drain connected to the first node, and a gate to which a signal corresponding to the input signal is fed. A second n-type transistor has a source and a gate both connected to VDDL and a drain connected to the first node.

    Power-on reset circuit
    5.
    发明授权
    Power-on reset circuit 失效
    上电复位电路

    公开(公告)号：US5517144A

    公开(公告)日：1996-05-14

    申请号：US257145

    申请日：1994-06-09

    Applicant: Katsuya Nakashima

    Inventor： Katsuya Nakashima

    IPC: H03K17/22 ,  H03K3/356 ,  H03K3/3565 ,  H03K3/281

    CPC classification number: H03K3/356008 ,  H03K3/3565

    Abstract: A power-on reset circuit provides the stable generation of a reset signal without being affected by the rising characteristic of a power-supply voltage. A flip-flop having a pair of cross-connected inverters is used, a common connection point between a diode and a capacitor connected to each other in series is connected to a node, which is one output of the flip-flop, an output signal at a node, which is another output of the flip-flip, is supplied to a reset pulse generator via an inverter, so that a reset pulse is generated based on a detected output signal change.

    Abstract translation: 上电复位电路可以稳定地产生复位信号，而不受电源电压上升特性的影响。 使用具有一对交叉连接的逆变器的触发器，将二极管和彼此串联连接的电容器之间的公共连接点连接到作为触发器的一个输出的节点，输出信号 在作为触发器的另一输出的节点处经由反相器提供给复位脉冲发生器，使得基于检测到的输出信号变化产生复位脉冲。

    Static inverter with controlled core saturation
    6.
    发明授权
    Static inverter with controlled core saturation 失效
    控制磁芯饱和的静态逆变器

    公开(公告)号：US4002999A

    公开(公告)日：1977-01-11

    申请号：US628564

    申请日：1975-11-03

    Applicant: Joseph P. Hesler ,  Samuel M. Korzekwa

    Inventor： Joseph P. Hesler ,  Samuel M. Korzekwa

    IPC: H02M7/44 ,  H02M7/5383 ,  H02M7/53846 ,  H02M7/53862 ,  H03K3/51 ,  H03K3/281

    CPC classification number: H02M7/53862 ,  H02M7/44 ,  H02M7/53846 ,  H03K3/51

    Abstract: A static inverter is disclosed for d.c. to a.c. conversion comprising a pair of switching semiconductor devices and a power transformer having primary, secondary and control windings associated with a double apertured linear magnetic core. Each aperture partitions the core cross section in a localized region into two branches. The primary and secondary power windings encircle the full core, which has a closed magnetic path, while the control windings are associated with only a branch. Means are provided to cause one branch to saturate before the other branch and before full core saturation. Saturation of one branch is used to reduce the regenerative feedback and increase the degenerative feedback to provide an advance turn off, allowing charge stored in the switching device to dissipate prior to the end of each conduction period. This mode of the feedback control avoids full core saturation and avoids overstressing the switching devices that full core saturation would produce. The arrangement permits one to develop high power outputs from relatively inexpensive power transistors.

    Abstract translation: 公开了一种静态逆变器，用于直流 到a.c. 转换器包括一对开关半导体器件和具有与双开孔线性磁芯相关联的初级，次级和控制绕组的电力变压器。 每个孔将局部区域中的核心横截面分成两个分支。 主功率和次级功率绕组环绕全磁芯，其具有闭合的磁路，而控制绕组仅与分支相关联。 提供装置以使一个分支在另一个分支之前和在全核饱和之前饱和。 使用一个分支的饱和度来减少再生反馈并增加退化反馈以提供提前关断，从而允许存储在开关装置中的电荷在每个导通周期结束之前消散。 这种反馈控制模式避免了全核饱和，并避免了过饱和的全核饱和产生的开关器件。 该装置允许从相对便宜的功率晶体管开发高功率输出。

    Cycling timer apparatus with automatic interruption and hold
    7.
    发明授权
    Cycling timer apparatus with automatic interruption and hold 失效
    自动中断和保持的循环计时器

    公开(公告)号：US3909635A

    公开(公告)日：1975-09-30

    申请号：US42765673

    申请日：1973-12-26

    Applicant: NIPPON KOGAKU KK

    Inventor： MAIDA OSAMU

    IPC: G03B17/42 ,  G03B19/18 ,  H03K3/03 ,  H03K3/282 ,  H03K3/64 ,  H03K17/28 ,  H03K5/13 ,  H03K3/281 ,  H03K5/04

    CPC classification number: H03K17/28 ,  G03B17/425 ,  G03B19/18 ,  H03K3/03 ,  H03K3/2823 ,  H03K3/64

    Abstract: Timers for controlling load circuits, such as motors in motordriven cameras, have ON and OFF intervals which can either be continuously repeated or automatically interrupted after various selected sequences of ON-OFF operations for thereafter holding the load circuit in an energized or de-energized state. The timers comprise a bi-stable circuit having complementary output signals and a pair of CR time-delay circuits for generating timedelayed signals in response to the output signals, the timedelayed signals being coupled to respective inputs of the bistable circuit for causing the bi-stable circuit to be alternately set in first and second states. A load responsive to one of the output signals is energized or de-energized in accordance with the state of the bi-stable circuit. An interrupter circuit responsive to one of the time-delayed signals causes the load to be continuously energized or de-energized after a selected ON-OFF sequence.

    Abstract translation: 用于控制负载电路的定时器，例如电动照相机中的电动机，具有ON和OFF间隔，其可以在各种所选择的ON-OFF操作序列之后连续重复或自动中断，此后将负载电路保持在通电或去激活状态， 通电状态。 定时器包括具有互补输出信号的双稳态电路和用于响应于输出信号产生时间延迟的信号的一对CR时间延迟电路，时间延迟的信号耦合到双稳态电路的相应输入 用于使双稳态电路交替地设置在第一和第二状态。 响应于其中一个输出信号的负载根据双稳电路的状态被激励或断电。 响应于其中一个时间延迟信号的断续器电路使得在所选择的开 - 关序列之后，负载被连续地通电或断电。

    Sense amplifier
    8.
    发明授权
    Sense amplifier 失效
    感应放大器

    公开(公告)号：US3879621A

    公开(公告)日：1975-04-22

    申请号：US35214373

    申请日：1973-04-18

    Applicant: IBM

    Inventor： CAVALIERE JOSEPH RICHARD ,  SCARPERO JR WILLIAM JOHN

    IPC: G11C11/41 ,  G11C11/409 ,  G11C11/419 ,  H03F3/18 ,  H03K5/02 ,  H03K19/017 ,  H03K3/281

    CPC classification number: G11C11/419 ,  H03K5/023

    Abstract: An FET sense amplifier for converting a double rail differential memory output signal to a full logic output signal, the amplifier comprising first and second pairs of FETs coupled together at a pair of common nodes. In one embodiment, first and second field effect transistors of the same conductive type are connected to respective ones of the nodes. A third field effect transistor of a second conductive type is connected to one of the pairs of FETs, the first, second and third field effect transistors are interconnected so that when the first and second transistors conduct the third transistor is cut off, and when the first and second transistors are cut off, the third transistor conducts.

    Abstract translation: 一种用于将双轨差分存储器输出信号转换为全逻辑输出信号的FET读出放大器，该放大器包括在一对公共节点处耦合在一起的第一和第二对FET。 在一个实施例中，相同导电类型的第一和第二场效应晶体管连接到相应的节点。 第二导电类型的第三场效应晶体管连接到FET对中的一个，第一，第二和第三场效应晶体管互连，使得当第一和第二晶体管导通第三晶体管被切断时，并且当 第一和第二晶体管被切断，第三晶体管导通。

    Divider circuits
    10.
    发明授权
    Divider circuits 失效
    分流电路

    公开(公告)号：US3816759A

    公开(公告)日：1974-06-11

    申请号：US25303472

    申请日：1972-05-12

    Applicant: SMITHS INDUSTRIES LTD

    Inventor： SHEPHERD B

    IPC: H03K3/281 ,  H03K23/22 ,  H03K23/30

    CPC classification number: H03K3/281

    Abstract: A divide-by-two divider circuit comprises first, second and third switch means each having a pair of regeneratively interconnected transistors. The first and second switch means are arranged to switch from a non-conductive state to a conducting state in response to, respectively, the application of, and the cessation of, a first of two successive input signals. The third switch means responds to the application of the second signal to switch from a non-conducting state to a conducting state and to initiate switching of the first and second switch means back to the non-conducting state, and the third switch means reverts to its non-conducting state in response to the cessation of said second signal.

    Abstract translation: 一个二分频分频器电路包括第一，第二和第三开关装置，每个具有一对再生互连的晶体管。 第一和第二开关装置被布置成响应于两个连续输入信号中的第一个的分别施加和停止而从非导通状态切换到导通状态。 第三开关装置响应于第二信号的应用从非导通状态切换到导通状态，并且启动第一和第二开关装置切换回非导通状态，并且第三开关装置恢复到 其响应于所述第二信号的停止而导致其不导通状态。

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