公开(公告)号：US09866204B1

公开(公告)日：2018-01-09

申请号：US15184395

申请日：2016-06-16

Applicant: Lockheed Martin Corporation

Inventor： Toshi Omori ,  Brandon R. Davis ,  Lloyd F. Linder ,  Victoria T. Pereira

IPC: H03K3/286 ,  H03K3/2885

CPC classification number: H03K3/2885

Abstract: A latch circuit providing isolated input current paths includes a pair of input transistors that receive a differential input signal. A plurality of steering transistors receive a portion of a differential clock signal. The latch circuit includes a positive output node and a negative output node. A first bypass input current path is associated with the first input transistor and is electrically isolated from the positive output node and the negative output node. A second bypass input current path associated with the second input transistor is also electrically isolated from the positive output node and the negative output node. In a latched state, the clock signal is operative to selectively bias the plurality of steering transistors such that current is steered to one of the first input current path or the second input current path, thereby being isolated from the output nodes.

公开(公告)号：US09559672B1

公开(公告)日：2017-01-31

申请号：US13863162

申请日：2013-04-15

Applicant: Marvell International Ltd.

Inventor： Vinay Chitturi ,  Oscar M. Siguenza

IPC: H03K3/289 ,  H03K3/286

CPC classification number: H03K3/289 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356156

Abstract: In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.

Abstract translation: 在一个或多个实施例中，集成电路包括可编程存储器，密钥生成模块和模块。 可编程存储器是保持第一键部分。 密钥生成模块使用来自可编程存储器的第一密钥部分和经由存储器接口接收的第二密钥部分来生成密钥。 该模块是使用密钥加密或解密数据。

公开(公告)号：US20150214933A1

公开(公告)日：2015-07-30

申请号：US14473922

申请日：2014-08-29

Applicant: Mentor Graphics Corporation

Inventor： Rajeev Sehgal ,  Srinivas Mandavilli ,  Pradish Mathews ,  Ajit Singh ,  Henry Potts

IPC: H03K3/286 ,  H03K19/0175 ,  H03K19/096

CPC classification number: H03K19/017509 ,  G01R19/16504 ,  G06F11/14 ,  H03K3/013 ,  H03K3/0375 ,  H03K3/2865 ,  H03K19/096

Abstract: This application discloses a system to detect meta-stable glitches in a signal, such as an output of latch or other storage element. The system can include a sampling circuit configured to sample an output of a storage element. The system can include a mono-shot circuit configured to monitor the output of the storage element and generate a pulse when the monitored output of the storage element differs from the sampled output. The system can include a drive circuit configured to generate a glitch signal based, at least in part, on the sampled output, and to output the glitch signal in response to the pulse from the mono-shot circuit. The system can include an error detection circuit configured to receive the sampled output from the sampling circuit and the glitch signal from the drive circuit, and to generate an error signal when the sampled output differs from the glitch signal.

Abstract translation: 本申请公开了一种用于检测诸如锁存器或其他存储元件的输出的信号中的元稳定毛刺的系统。 该系统可以包括被配置为对存储元件的输出进行采样的采样电路。 该系统可以包括被配置为监视存储元件的输出并且当监视的存储元件的输出与采样输出不同时产生脉冲的单触发电路。 该系统可以包括驱动电路，其被配置为至少部分地基于采样输出产生毛刺信号，并且响应于来自单声道电路的脉冲输出毛刺信号。 该系统可以包括错误检测电路，其被配置为从采样电路接收采样的输出和来自驱动电路的毛刺信号，并且当采样输出与毛刺信号不同时产生误差信号。

公开(公告)号：US07256634B2

公开(公告)日：2007-08-14

申请号：US11176918

申请日：2005-07-06

Applicant: Robert Paul Masleid

Inventor： Robert Paul Masleid

IPC: H03K3/286 ,  H03K3/356

CPC classification number: H03K3/356121 ,  G06F9/3869

Abstract: An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an input signal through as an output signal, and a pulse width/inhibit component coupled to the drive component. The latch further includes a reset threshold component coupled to the drive component for inhibiting oscillation of the drive component, and a latch component for passing the present state of the input signal to the output signal when configured as the repeater state and for maintaining the previous state of the output signal during transitions of a clock signal when configured as the latch state.

公开(公告)号：US07202724B2

公开(公告)日：2007-04-10

申请号：US10997958

申请日：2004-11-29

Applicant: Min-Su Kim

Inventor： Min-Su Kim

IPC: H03K3/286 ,  H03K3/356 ,  H03K3/00 ,  G06F1/04

CPC classification number: H03K5/151 ,  H03K3/037 ,  H03K5/135 ,  H03K5/1534

Abstract: A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

公开(公告)号：US07173456B2

公开(公告)日：2007-02-06

申请号：US10730168

申请日：2003-12-06

Applicant: James R. Lundberg

Inventor： James R. Lundberg

IPC: H03K19/096 ,  H03K3/286

CPC classification number: H03K19/0963

Abstract: A dynamic logic return-to-zero (RTZ) latching mechanism including a complementary pair of evaluation devices responsive to a clock signal, a dynamic evaluator, delayed inversion logic, and latching logic. The dynamic evaluator is coupled between the complementary pair of evaluation devices at a pre-charged node and evaluates a logic function based on at least one input data signal. The latching logic asserts the logic state of an output node based on the state of the pre-charged node during an evaluation period between an operative edge of the clock signal and the next edge of an evaluation complete signal, which is a delayed and inverted version of the clock signal. The output node is returned to zero between evaluation periods. A footless latching domino circuit may be added to convert the RTZ output to a registered output signal.

Abstract translation: 动态逻辑归零（RTZ）锁存机制包括响应于时钟信号的一对互补的评估装置，动态评估器，延迟反转逻辑和锁存逻辑。 动态评估器在预充电节点处耦合在互补的评估装置对之间，并基于至少一个输入数据信号来评估逻辑功能。 锁定逻辑在时钟信号的操作边缘与评估完成信号的下一个边缘之间的评估周期期间基于预充电节点的状态来断言输出节点的逻辑状态，该评估完成信号是延迟和反向版本 的时钟信号。 输出节点在评估周期之间返回到零。 可以添加一个无脚锁定多米诺骨牌电路，以将RTZ输出转换为已注册的输出信号。

公开(公告)号：US07167033B2

公开(公告)日：2007-01-23

申请号：US11154114

申请日：2005-06-15

Applicant: Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

Inventor： Yukio Arima ,  Takahiro Yamashita ,  Koichiro Ishibashi

IPC: H03K3/356 ,  H03K3/286

CPC classification number: H03K3/0375 ,  H03K3/356156 ,  H03K3/3565 ,  H03K17/162 ,  H03K17/165 ,  H03K19/00338

Abstract: A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be put out, it is corrected by a pull-up path or a pull-down path, and when a soft error occurs in the data in the pull-up path or the pull-down path, the error data in the pull-up path or the pull-down path is prevented from affecting each other, as well as turning off the correcting function to prevent the influence on the data to be put out.

Abstract translation: 已经公开了一种数据保持电路，其中即使发生软错误，也可以进行校正，可以保持正常值，配置简单，并且能够进行高速操作。 在该电路中，当要放出的数据发生软错误时，通过上拉路径或下拉路径进行校正，并且当在上拉路径中的数据或 下拉路径，防止上拉路径或下拉路径中的误差数据彼此相互影响，以及关闭校正功能以防止对数据的影响。

公开(公告)号：US07164302B1

公开(公告)日：2007-01-16

申请号：US10874041

申请日：2004-06-21

Applicant: Ilyas Elkin

Inventor： Ilyas Elkin

IPC: H03K3/356 ,  H03K3/286

CPC classification number: H03K3/012 ,  H03K3/013 ,  H03K3/0375 ,  H03K3/356121

Abstract: A one gate delay output noise insensitive latch includes an input node, an output node, a storage node, a not storage node, and a data clock line. A primary latch element is connected to the input node, the output node, and the data clock line. A mirror primary latch element is connected to the input node in parallel with the primary latch element, to the storage node, and to the data clock line. A weak keeper is connected to the storage node and to the not storage node. A strong enabled tri-state keeper is connected to the not storage node, to the data clock line, and to the output node. The input node is either a dynamic data input node or a static data input node. Optionally, the weak keeper is also clock enabled.

Abstract translation: 一个门延迟输出噪声不敏感锁存器包括输入节点，输出节点，存储节点，非存储节点和数据时钟线。 主锁存元件连接到输入节点，输出节点和数据时钟线。 镜主主锁存元件与主闩锁元件并联连接到输入节点，连接到存储节点和数据时钟线。 弱守护者连接到存储节点和非存储节点。 强有力的三态保持器连接到非存储节点，数据时钟线和输出节点。 输入节点是动态数据输入节点或静态数据输入节点。 可选地，弱守门员也启用时钟。

公开(公告)号：US20050237098A1

公开(公告)日：2005-10-27

申请号：US10878142

申请日：2004-06-28

Applicant: Nak Park

Inventor： Nak Park

IPC: G11C7/00 ,  H03K3/033 ,  H03K3/286 ,  H03K3/355

CPC classification number: H03K3/033 ,  H03K3/355

Abstract: The disclosure is directed to an internal pulse generator outputting a signal with a constant pulse width nevertheless of a frequency of an input signal, including a first PMOS transistor, a PMOS second transistor and an NMOS transistor which are connected between a power supply voltage and a ground voltage in series, a latch and an inverter which are connected between an output terminal and a first node as a drain of the NMOS transistor, and a Y-time delay circuit connected between the output terminal and a second node that is a common gate of the PMOS and NMOS transistors.

Abstract translation: 本公开涉及内部脉冲发生器，其输出具有恒定脉冲宽度的信号，该信号具有输入信号的频率，包括第一PMOS晶体管，PMOS第二晶体管和NMOS晶体管，其连接在电源电压和 连接在输出端子和第一节点之间的串联接地电压，锁存器和反相器，作为NMOS晶体管的漏极，以及连接在输出端子和作为公共栅极的第二节点之间的Y延迟电路 的PMOS和NMOS晶体管。

公开(公告)号：US06943605B2

公开(公告)日：2005-09-13

申请号：US10334436

申请日：2002-12-31

Applicant: Paul J. Thadikaran ,  Nasser A. Kurd

Inventor： Paul J. Thadikaran ,  Nasser A. Kurd

IPC: G01R31/3185 ,  G06F11/267 ,  H03K3/037 ,  H03K3/12 ,  H03K3/286

CPC classification number: G06F11/2236 ,  G01R31/318541

Abstract: According to some embodiments, scan cell designs are provided for a double-edge-triggered flip-flop.

Abstract translation: 根据一些实施例，为双边沿触发的触发器提供扫描单元设计。