公开(公告)号：US20240267036A1

公开(公告)日：2024-08-08

申请号：US18615361

申请日：2024-03-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

Inventor： Huaixin XIAN ,  Qingchao MENG ,  Yang ZHOU ,  Shang-Chih HSIEH

IPC: H03K3/037 ,  H01L27/105 ,  H01L29/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H03K3/288 ,  H03K3/289 ,  H03K3/356 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  H01L27/105 ,  H01L29/02 ,  H01L29/06 ,  H01L29/1075 ,  H01L29/41725 ,  H03K3/288 ,  H03K3/289 ,  H03K3/356017 ,  H03K3/356104 ,  H03K3/356113 ,  H03K3/356147 ,  H03K3/3562 ,  H03K3/35625

Abstract: An integrated circuit includes a first time delay circuit, a second time delay circuit, and a master-slave flip-flop having a gated input circuit and a transmission gate. The transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate. The gated input circuit is configured to have an input transmission state controlled by the third clock signal at the second output of the second time delay circuit. The second time delay circuit further includes a second gate-conductor and a second gate via-connector in direct contact with the second gate-conductor. The second gate-conductor intersects a first-type active region structure and a second-type active region structure in a second area, and wherein at least a portion of the second gate via-connector is atop the second-type active region structure

公开(公告)号：US20230048735A1

公开(公告)日：2023-02-16

申请号：US17976187

申请日：2022-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung Shen ,  Chi-Lin Liu ,  Stefan Rusu ,  Yan-Hao Chen ,  Jerry Chang-Jui Kao

IPC: H03K3/012 ,  H03K3/0233 ,  H03K3/289 ,  H03K3/037 ,  H03K3/3562 ,  H03K3/356

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US11552622B1

公开(公告)日：2023-01-10

申请号：US17702295

申请日：2022-03-23

Applicant: SambaNova Systems, Inc.

Inventor： Ha Pham ,  Jinuk Shin ,  Yukio Otaguro

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/037 ,  H03K19/20

Abstract: A master-slave flip-flop includes a first latch, a second latch and a tristate driver. The first latch has a combined input/output that is coupled with a common node, a pm output, and an nm output. The tristate driver has pm and nm inputs coupled with the pm and nm outputs of the first latch, and a tristate output coupled with the common node. A pm input signal prevents the tristate driver from pulling the common node high, and an nm input signal prevents the tristate driver from pulling the common node low. The second latch is directly coupled with the common node. The first latch generates an nm signal and a pm signal in response to a signal on the first latch clk input and a state of the common node, wherein the pm signal and the nm signal have opposite polarities when the signal on the first latch clk input has a first value, and equal polarities when the signal on the first latch clk input has a second value.

公开(公告)号：US20210175876A1

公开(公告)日：2021-06-10

申请号：US17180379

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia LAI ,  Meng-Hung SHEN ,  Chi-Lin LIU ,  Stefan RUSU ,  Yan-Hao CHEN ,  Jerry Chang-Jui KAO

IPC: H03K3/012 ,  H03K3/0233 ,  H03K3/289 ,  H03K3/037 ,  H03K3/3562 ,  H03K3/356

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US10326430B2

公开(公告)日：2019-06-18

申请号：US15485595

申请日：2017-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chia Lai ,  Meng-Hung Shen ,  Chi-Lin Liu ,  Stefan Rusu ,  Yan-Hao Chen ,  Jerry Chang-Jui Kao

IPC: H03K3/3562 ,  H03K3/012 ,  H03K3/0233 ,  H03K3/289 ,  H03K3/037 ,  H03K3/356

Abstract: A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.

公开(公告)号：US09762212B1

公开(公告)日：2017-09-12

申请号：US15245896

申请日：2016-08-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： William V. Huott ,  Ricardo H. Nigaglioni ,  Hagen Schmidt ,  James D. Warnock

IPC: H03K3/289 ,  H03K3/037 ,  H03K19/20 ,  G06F1/12

CPC classification number: H03K3/0372 ,  G06F1/12 ,  G06F13/1673 ,  G06F13/4243 ,  H03K19/20

Abstract: Aspects include a computer-implemented method for initializing scannable and non-scannable latches from a clock buffer. The method includes receiving a clock signal; receiving control signals including a hold signal, a scan enable signal, and a non-scannable latch force signal; responsive to receiving a low input from the hold signal and the scan enable signal, outputting a high signal from a functional clock port on a next cycle; responsive to receiving a high input from the scan enable signal and a low input from the hold signal, outputting a high slave latch scan clock signal on the next cycle; responsive to receiving a high input from the hold signal and the scan enable signal, outputting a high master latch clock signal on the next clock cycle; and responsive to receiving a high input from the non-scannable latch force signal, outputting a low master latch clock signal on a current cycle.

公开(公告)号：US09634649B2

公开(公告)日：2017-04-25

申请号：US14792276

申请日：2015-07-06

Applicant: NXP B.V.

Inventor： Juan Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Sebastien Antonius Josephus Fabrie

IPC: H03K3/289 ,  H03K3/356 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012 ,  H03K3/037 ,  H03K19/0016

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.

公开(公告)号：US09628062B1

公开(公告)日：2017-04-18

申请号：US15180092

申请日：2016-06-13

Applicant: NXP B.V.

Inventor： Van-Loi Le ,  Tae-Hyoung Kim ,  Juhui Li ,  Alan Yeow Khai Chang

IPC: H03K3/289 ,  H03K5/19 ,  H03K3/3562

CPC classification number: H03K5/19 ,  H03K3/012 ,  H03K3/35625

Abstract: A 24-transistor D flip-flop circuit operates in a sampling mode when a clock signal has a first voltage state, and a holding mode when the clock signal has a second voltage state. The flip-flop circuit includes an internal control node coupled to a reference voltage node by way of a transistor controllable to couple the internal control node to the reference voltage node when the clock signal has the second voltage state. The flip-flop has very low power dissipation as it includes a 4-transistor change-sense component to detect changes in input data. The change-sense component is coupled in series with the transistor and receives an indication of an input voltage state of the flip-flop circuit and an indication of an output voltage state of the flip-flop circuit, and inhibits toggling of the internal control node if the indicated input voltage state and the indicated output voltage state are the same.

公开(公告)号：US09584121B2

公开(公告)日：2017-02-28

申请号：US14736213

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Zhengyu Duan ,  Steven James Dillen ,  Animesh Datta

IPC: H03K3/289 ,  H03K19/00 ,  H03K3/3562

CPC classification number: H03K19/0013 ,  G01R31/318541 ,  G06F1/04 ,  H03K3/037 ,  H03K3/35625

Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

Abstract translation: MOS器件包括配置有一个锁存器反馈F并被配置为接收锁存器输入I和锁存时钟C的第一锁存器。第一锁存器被配置为输出Q，其中输出Q是CF，IF和IC的函数 并且锁存反馈F是输出Q的函数。第一锁存器可以包括串联堆叠的第一组晶体管，其中第一组晶体管包括至少五个晶体管。 MOS器件还可以包括耦合到第一锁存器的第二锁存器。 第二锁存器可以被配置为扫描模式下的锁存器和功能模式中的脉冲锁存器。 第一锁存器可以作为主锁存器操作，并且第二锁存器可以在扫描模式期间作为从锁存器操作。

公开(公告)号：US09306545B2

公开(公告)日：2016-04-05

申请号：US14154757

申请日：2014-01-14

Applicant: ARM LIMITED

Inventor： Anil Kumar Baratam

IPC: H03K3/289 ,  H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35625

Abstract: A master-slave flip-flop circuit with a master latch and slave latch has clock generating circuitry which generates a gated clock signal based on the clock signal and a gating control signal. When the gating control signal has a first value, then the gated clock signal has a value dependent on the clock signal, while when the gating control signal has a second value then the gated clock signal has a fixed value independent of the clock signal. At least one component of the master-slave flip-flop circuit is controlled by the gated clock signal so that dynamic switching power can be reduced. The gating control signal is dependent on the input signal or a signal within the master latch and is independent of a slave signal in the slave latch and the output signal of the flip-flop.

Abstract translation: 具有主锁存器和从锁存器的主从触发器电路具有基于时钟信号和门控控制信号产生门控时钟信号的时钟发生电路。 当选通控制信号具有第一值时，门控时钟信号具有取决于时钟信号的值，而当门控控制信号具有第二值时，门控时钟信号具有与时钟信号无关的固定值。 主从触发器电路的至少一个组件由门控时钟信号控制，从而可以降低动态开关功率。 门控控制信号取决于输入信号或主锁存器内的信号，与从锁存器中的从属信号和触发器的输出信号无关。