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    OSCILLATOR MONITORING CIRCUITS FOR DIFFERENT OSCILLATOR DOMAINS
    1.
    发明公开
    OSCILLATOR MONITORING CIRCUITS FOR DIFFERENT OSCILLATOR DOMAINS 审中-公开

    公开(公告)号：US20240364353A1

    公开(公告)日：2024-10-31

    申请号：US18768179

    申请日：2024-07-10

    申请人： Allegro MicroSystems, LLC

    发明人： Florencia Ferrer ,  Lucas Intile ,  Juan Manuel Cesaretti ,  Nicolás Rigoni

    IPC分类号： H03L7/099 ,  H03D13/00 ,  H03K3/12

    CPC分类号： H03L7/0991 ,  H03D13/001 ,  H03K3/12

    摘要： Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

    Systems and methods for PLL gain calibration
    3.
    发明授权
    Systems and methods for PLL gain calibration 有权

    公开(公告)号：US12132490B2

    公开(公告)日：2024-10-29

    申请号：US18121404

    申请日：2023-03-14

    申请人： Apple Inc.

    发明人： Karim M Megawer ,  Jongmin Park ,  Thomas Mayer

    IPC分类号： H03L7/083 ,  H03L7/081 ,  H03L7/195

    CPC分类号： H03L7/083 ,  H03L7/0818 ,  H03L7/195

    摘要： This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

    Coarse-Mover with Sequential Finer Tuning Step
    5.
    发明公开
    Coarse-Mover with Sequential Finer Tuning Step 审中-公开

    公开(公告)号：US20240348256A1

    公开(公告)日：2024-10-17

    申请号：US18753394

    申请日：2024-06-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Tsung-Hsien Tsai ,  Jason Hsu ,  Ruey-Bin Sheen

    IPC分类号： H03L7/099 ,  H03L7/187

    CPC分类号： H03L7/0992 ,  H03L7/187

    摘要： A tuning array selection circuit, together with a decoder and a voltage controlled oscillator (VCO), can be employed to overcome some disadvantages of previous methods of phase locked loops. For example, a VCO can include a coarse tuning array and a fine tuning array. A coarse tuning array can be used to tune a VCO to generate a signal within a wide frequency range. A fine tuning array can be used to tune a VCO to generate a signal within a narrow frequency range. In one embodiment, the narrow frequency range is within the wide frequency range. The tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.

    FREQUENCY DOUBLER WITH DUTY CYCLE ESTIMATOR, DUTY CYCLE CORRECTOR, AND T/4 DELAY GENERATOR
    8.
    发明公开
    FREQUENCY DOUBLER WITH DUTY CYCLE ESTIMATOR, DUTY CYCLE CORRECTOR, AND T/4 DELAY GENERATOR 审中-公开

    公开(公告)号：US20240339996A1

    公开(公告)日：2024-10-10

    申请号：US18295376

    申请日：2023-04-04

    申请人： Silicon Laboratories Inc.

    发明人： Patan Imran Khan ,  Hariharan Ganapathy Raman ,  Rahul Reghu

    IPC分类号： H03K5/156 ,  H03L7/081

    CPC分类号： H03K5/1565 ,  H03L7/0814

    摘要： A clock doubler circuit doubles the frequency of an input clock signal. The input clock signal is supplied to a duty cycle corrector (DCC) circuit, which generates a DCC output signal having a duty cycle corrected to fifty percent and has a frequency that equals the input frequency. A T/4 delay circuit receives the input clock signal and generates a T/4 delay output signal that has a delay of T/4 from the DCC output signal and has the same frequency as the input clock signal. T/4 is one quarter of a period of the input clock signal. An XOR gate combines the DCC output signal and the T/4 delay output signal to generate an output clock signal that is twice the frequency of the input clock signal. A duty cycle estimator generates correction factors used to generate the T/4 delay output signal and the DCC output signal.

    Digital clock and data recovery circuit and feedback loop circuit including the same
    9.
    发明授权
    Digital clock and data recovery circuit and feedback loop circuit including the same 有权

    公开(公告)号：US12113887B2

    公开(公告)日：2024-10-08

    申请号：US17881417

    申请日：2022-08-04

    申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    发明人： Seon-Ho Han ,  Young-Su Kwon

    IPC分类号： H04L7/033 ,  H03L7/08 ,  H03L7/093

    CPC分类号： H04L7/033 ,  H03L7/0807 ,  H03L7/093

    摘要： Disclosed are a digital CDR circuit and a feedback loop circuit including the same. The digital CDR circuit includes a phase detector that receives an input signal and outputs a phase detection result signal corresponding to a determination result for a sampling time based on the input signal, a charge pump that receives the phase detection result signal and outputs an amplified signal obtained by multiplying the phase detection result signal by a gain, a loop filter that receives the amplified signal and filters the amplified signal to output a filtered signal, and a phase shift control code generator that generates a control signal for controlling a phase of a signal based on the filtered signal, and the input signal includes plural data signals and plural error signals, and the data signals and the error signals are digital signals which are quantized based on a signal magnitude.