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    Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods
    1.
    发明授权
    Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods 有权

    公开(公告)号：US12212327B2

    公开(公告)日：2025-01-28

    申请号：US18114847

    申请日：2023-02-27

    Applicant: Microsoft Technology Licensing, LLC

    Inventor： Ping Lu ,  Bupesh Pandita ,  Minhan Chen

    IPC: H03L7/085 ,  G04F10/00 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107

    Abstract: In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.

    Methods and devices for TDC resolution improvement
    2.
    发明授权
    Methods and devices for TDC resolution improvement 有权

    公开(公告)号：US12191871B2

    公开(公告)日：2025-01-07

    申请号：US17355217

    申请日：2021-06-23

    Applicant: Intel Corporation

    Inventor： Evgeny Shumaker ,  Elan Banin ,  Ofir Degani ,  Gil Horovitz

    IPC: H03L7/24 ,  G04F10/00 ,  H03L7/085 ,  H03L7/099

    Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.

    Time-to-digital converter stop time control
    4.
    发明授权
    Time-to-digital converter stop time control 有权

    公开(公告)号：US12170522B2

    公开(公告)日：2024-12-17

    申请号：US18175683

    申请日：2023-02-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Marius Moe ,  Tarjei Aaberge

    IPC: H03L7/085 ,  H03K3/03 ,  H03K5/14 ,  H03L7/081 ,  G04F10/00 ,  H03K5/00

    Abstract: In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

    Period error correction in digital frequency locked loops
    5.
    发明授权
    Period error correction in digital frequency locked loops 有权

    公开(公告)号：US12149253B2

    公开(公告)日：2024-11-19

    申请号：US18114595

    申请日：2023-02-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Janne Matias Pahkala

    IPC: H03L7/093 ,  H03L7/085 ,  H03L7/099 ,  G01S7/03 ,  H02M3/02

    Abstract: In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.

    Fractional divider with duty cycle regulation and low subharmonic content
    7.
    发明授权
    Fractional divider with duty cycle regulation and low subharmonic content 有权

    公开(公告)号：US12101095B2

    公开(公告)日：2024-09-24

    申请号：US18317582

    申请日：2023-05-15

    Applicant: Analog Devices International Unlimited Company

    Inventor： Justin L. Fortier ,  Benjamin Philip Walker

    IPC: H03L7/197 ,  H03L7/085 ,  H03L7/185

    CPC classification number: H03L7/1974 ,  H03L7/085 ,  H03L7/185

    Abstract: Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

    Clock Frequency Limiter
    8.
    发明公开
    Clock Frequency Limiter 审中-公开

    公开(公告)号：US20240305303A1

    公开(公告)日：2024-09-12

    申请号：US18664811

    申请日：2024-05-15

    Applicant: Apple Inc.

    Inventor： Jose A. Tierno ,  Ajay M. Rao

    IPC: H03L7/083 ,  H03L7/085 ,  H03L7/099

    CPC classification number: H03L7/083 ,  H03L7/085 ,  H03L7/0991

    Abstract: A receiver circuit that limits the frequency of a clock signal used in a computer system is disclosed. An embodiment of the receiver circuit includes a front-end circuit configured to generate an equalized signal, a clock generator circuit configured to generate a clock signal using a plurality of samples of the equalized signal, and a measurement circuit. The measurement circuit is configured to monitor a frequency of the clock signal and activate an indication signal in response to determining that the frequency of the clock signal exceeds a threshold frequency. In response to activation of the indication signal, the clock generator circuit is configured to set the frequency of the clock signal to a particular frequency.

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