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公开(公告)号：US11641207B2
公开(公告)日：2023-05-02
申请号：US17668394
申请日：2022-02-10
申请人： ZHEJIANG UNIVERSITY
发明人： Zhiwei Xu , Jiangbo Chen , Jiabing Liu , Hui Nie , Zhihao Lv , Chunyi Song
摘要： Disclosed is a fast lock phase-locked loop circuit for avoiding cycle slip, which belongs to the technical field of integrated circuits. The fast lock phase-locked loop circuit includes a phase frequency detector, a charge pump, an intermediate stage circuit, a loop filter, a voltage-controlled oscillator and a frequency divider. The phase frequency detector, the charge pump, the intermediate stage circuit, the loop filter and the voltage-controlled oscillator are connected in sequence; an output OUT end of the voltage-controlled oscillator is connected with an input IN end of frequency divider, and an output OUT end of the frequency divider is connected with an input IN end of the phase frequency detector to form a feedback path. The output clock frequency of the VCO and the expected frequency, i.e., the reference clock frequency and the feedback clock frequency, are prevented from being too close when the loop is started.
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公开(公告)号：US11626882B1
公开(公告)日：2023-04-11
申请号：US17750792
申请日：2022-05-23
申请人： VIAVI SOLUTIONS INC.
摘要： A wide band frequency synthesizer may include a primary phase-locked loop (PLL) to receive a signal that include a local signal and a VCO signal mixed together and to generate the tuning voltage based on a phase comparison of the local signal and the VCO signal. The local signal may be obtained from a reference signal through frequency multiplication. If the primary PLL fails to lock onto an output frequency, a secondary PLL (acquisition circuit) may be switched in performing a phase comparison between the reference signal and the VCO signal to generate the tuning voltage. The secondary PLL may then provide the tuning voltage to an output of the primary PLL.
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公开(公告)号：US20230093529A1
公开(公告)日：2023-03-23
申请号：US17941767
申请日：2022-09-09
申请人： Apple Inc.
发明人： Hongrui Wang , Abbas Komijani
摘要： Voltage-controlled oscillation circuitry includes multiple cores and multiple mode or gain boosters coupled between the multiple cores. To prevent an undesired operating mode of the voltage-controlled oscillation circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), the mode boosters may increase a desired gain of the desired operating mode and decrease an undesired gain of the undesired operating modes. In particular, mode boosters coupled to terminals of the cores that are associated with the desired operating mode may be enabled, while mode boosters coupled to terminals of the cores that are associated with the undesired operating mode may be disabled.
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公开(公告)号：US11601089B1
公开(公告)日：2023-03-07
申请号：US17463406
申请日：2021-08-31
摘要： A temperature compensated oscillator circuit includes a first oscillator, a second oscillator, a first divider, a second divider, a frequency ratio circuit, and a temperature compensation circuit. The first divider is coupled to the first oscillator, and is configured to divide a frequency of a first oscillator signal generated by the first oscillator. The second divider is coupled to the second oscillator, and is configured to divide a frequency of a second oscillator signal generated by the second oscillator. The frequency ratio circuit is coupled to the first divider and the second divider, and is configured to determine a frequency ratio of an output of the first divider to an output of the second divider. The temperature compensation circuit is coupled to the frequency ratio circuit and the first oscillator, and is configured to generate a compensated frequency based on the frequency ratio and the first oscillator signal.
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公开(公告)号：US11595051B2
公开(公告)日：2023-02-28
申请号：US17708944
申请日：2022-03-30
发明人： Tengxiao Jiang , Zhiyu Zhuang , Yiren Huang
摘要： Disclosed is a frequency dividing circuit, a frequency dividing method and a phase locked loop. The frequency dividing circuit comprises: a clock selection unit outputting a first clock signal, select a second clock signal lagging behind the first clock signal by (½-1/M) of one phase; an integer frequency dividing unit performing frequency division on the first clock signal to provide a frequency-divided clock signal; a trigger unit triggering the frequency-divided clock signal according to the second clock signal to obtain a modulation clock signal; a switching signal unit providing a switching signal according to the modulation clock signal and a preset target output frequency. The clock selection unit selects and further outputs a third clock signal as the first clock signal according to the target phase selection information, to adjust the frequency of the frequency-divided clock signal, reduce noise and improve loop bandwidth of the phase locked loop.
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公开(公告)号：US11595049B1
公开(公告)日：2023-02-28
申请号：US17710650
申请日：2022-03-31
发明人： Janne Matias Pahkala
摘要： In some examples, a digital frequency locked loop (DFLL) device includes a phase frequency detector (PFD) configured to receive a reference clock signal and an indicator of a primary clock signal and to determine differences between periods of the reference clock signal and the indicator. The DFLL also includes a controller coupled to the PFD. The controller is configured to store digital signals indicating a first and a second of the differences determined by the PFD, determine a period error by subtracting the second difference from the first difference, and compare the period error to a programmed threshold. The DFLL also includes a digitally controlled oscillator (DCO) coupled to the controller, the DCO configured to provide the primary clock signal having a frequency adjusted based on the comparison.
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7.发明授权公开(公告)号：US11595048B1
公开(公告)日：2023-02-28
申请号：US17704542
申请日：2022-03-25
发明人： Avri Harush
摘要： A digital phase-locked loop (DPLL) includes a time-to-digital converter (TDC) to generate a multi-bit code based on a phase error between a reference clock and a feedback clock, a digital loop filter (DLF) coupled to the TDC, a digitally-controlled oscillator (DCO) circuit coupled to the DLF and to generate an output signal that is convertible to the feedback clock, and a logic component coupled to an input of the DCO circuit. The logic component is to: trigger, in response to detecting a power on of the DPLL circuit, a switch to decouple the DLF from the DCO circuit; determine, from the reference clock, a target frequency; measure a frequency of the feedback clock; and iteratively generate, based on the frequency during each iteration, a set of digital bits to the input of the DCO circuit that successively causes the frequency to converge towards the target frequency.
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公开(公告)号：US11579273B2
公开(公告)日：2023-02-14
申请号：US17570120
申请日：2022-01-06
发明人： Marco Passoni , Niccolò Petrini
IPC分类号： G01S7/52 , B06B1/06 , G01S7/524 , G01S7/527 , G01S15/10 , G01S15/931 , H01L41/09 , H03L7/093
摘要： A method of operating electro-acoustical transducers such as PMUTs involves applying to the transducer an excitation signal over an excitation interval, acquiring at the transducer a ring-down signal indicative of the ring-down behavior of the transducer after the end of the excitation interval, and calculating, as a function of said ring-down signal, a resonance frequency of the electro-acoustical transducer. A bias voltage of the electro-acoustical transducer can be controlled as a function of the resonance frequency. An acoustical signal received can be transduced into an electrical reception signal and a damping parameter of the electro-acoustical transducer can be calculated as a function of the ring-down signal so that a cross-correlation reference signal can be synthesized as a function of the resonance frequency and the damping ratio of the electro-acoustical transducer. Such a cross-correlation reference signal can be used for cross-correlation with the electrical reception signal to improve the reception quality.
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公开(公告)号：US11563436B2
公开(公告)日：2023-01-24
申请号：US17863708
申请日：2022-07-13
发明人： Gagan Midha , Kallol Chatterjee , Anand Kumar , Ankit Gupta
摘要： A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.
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公开(公告)号：US20230006682A1
公开(公告)日：2023-01-05
申请号：US17663217
申请日：2022-05-13
发明人： Raja Prabhu J , Sandeep Sasi , Harshavardhan Reddy
摘要： Enhancing the accuracy in compensating errors caused by a reference signal with unequal successive periods in a fractional-N phase locked loop (PLL). A compensation block generates a compensation factor, and is implemented based on a correction block and a filter. The correction block generates a correction signal containing a first frequency correction factor and a second frequency correction factor for a first period and a second period constituting each pair of successive periods, with the correction signal also containing a noise component at direct current (DC). The filter operates to remove the noise component at DC from the correction signal to generate a compensation factor containing the first frequency correction factor and the second frequency correction factor. The compensation factor thus generated may be provided as an input to a division factor generator of a frequency divider block of the PLL, potentially resulting in zero error frequency synthesis.
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