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1.发明授权公开(公告)号：US12224759B2
公开(公告)日：2025-02-11
申请号：US17863167
申请日：2022-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaerin Lee , Yang Azevedo Tavares , Minjae Lee , Kyeongkeun Kang
Abstract: An apparatus and a method of correcting a mismatch of a time-interleaved analog-to-digital converter are provided. The apparatus may include: a time-interleaved analog-to-digital converter configured to receive a non-return-to-zero (NRZ) signal in a correction mode and generate a first output signal, and including a plurality of analog-to-digital converters; and a mismatch corrector configured to generate a second output signal by processing the first output signal of the time-interleaved analog-to-digital converter based on parameters, wherein the parameters may be generated based on the first output signal of the time-interleaved analog-to-digital converter in the correction mode, and a period of the NRZ signal may be different from a product of a sampling period of the time-interleaved analog-to-digital converter and a number of the plurality of analog-to-digital converters included in the time-interleaved analog-to-digital converter.
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公开(公告)号：US12218679B2
公开(公告)日：2025-02-04
申请号：US18146641
申请日：2022-12-27
Applicant: Infineon Technologies AG
Inventor： Dan Ioan Dumitru Stoica , Constantin Crisu , Constantin Stroi , Vlad Buiculescu , Matthias Böhm , Alessandro Caspani , Cesare Buffa , Franz Michael Darrer
IPC: H03M1/10 , G10L21/0232 , H03M1/06 , H03M1/34
Abstract: A sensor circuit, having a startup phase and an operation phase, includes: a sensor configured to generate a sensor signal based on a measured property, wherein the sensor signal has a frequency spectrum defined by a first frequency and a second frequency that is greater than the first frequency; a signal processing circuit including an analog-to-digital converter (ADC) configured to convert the sensor signal into a digital sensor signal; and an offset diagnosis circuit. The offset diagnosis circuit includes: a low pass filter having a cutoff frequency less than the first frequency and configured to generate a filtered signal based on the digital sensor signal; an offset register configured to store a startup signal value of the filtered signal during the startup phase; and an offset comparator circuit configured to set a threshold range based on the startup signal value for use during the operation phase.
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公开(公告)号：US20250038755A1
公开(公告)日：2025-01-30
申请号：US18910306
申请日：2024-10-09
Inventor： Ahmed Elkholy , Jun Cao , Adesh Garg
Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
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公开(公告)号：US12212332B2
公开(公告)日：2025-01-28
申请号：US18105675
申请日：2023-02-03
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Hsuan-Ting Ho , Shih-Hsiung Huang , Liang-Wei Huang
Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit. The echo calibration circuit makes response coefficients converge according to the error signal and pseudo-noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates codeword offset table according to the offset.
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公开(公告)号：US12206426B2
公开(公告)日：2025-01-21
申请号：US17358044
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Albert Molina , Martin Clara , Kameran Azadet
Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).
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Patent Agency Ranking
公开(公告)号：US20250015809A1
公开(公告)日：2025-01-09
申请号：US18348994
申请日：2023-07-07
Applicant: The Boeing Company
Inventor： Alfio Zanchi , Casey Gooch
IPC: H03M1/06
Abstract: Examples are disclosed that relate to detection of single event effects on an analog-to-digital converter. In one example, an electronic device includes an analog-to-digital converter and an event detection engine co-located on the same integrated circuit. The analog-to-digital converter is configured to receive an analog signal and output a set of digital signals representative of the analog signal. The event detection engine is configured to receive the set of digital signals from the analog-to-digital converter, and for each digital signal of the set of digital signals, compare a magnitude of the digital signal with a threshold, and output an error signal indicating a single-event error of the analog-to-digital converter based at least on the magnitude of the digital signal exceeding the threshold.
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公开(公告)号：US12184295B2
公开(公告)日：2024-12-31
申请号：US17880417
申请日：2022-08-03
Applicant: Socionext Inc.
Inventor： Sandeep Santhosh Kumar , Jayaraman Kumar , Armin Jalili Sebardan , Martin Wilson
IPC: H03M1/06
Abstract: Analogue-to-digital converter, ADC, circuitry including: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry including a compensation capacitor and configured, in a precharge operation, to connect the compensation capacitor so that the compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry compensates for the charge drawn from the first voltage reference, REF1, by the successive-approximation circuitry.
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公开(公告)号：US20240413832A1
公开(公告)日：2024-12-12
申请号：US18482804
申请日：2023-10-06
Inventor： Sunghun YANG , Jaehun Jeong , Youngwon Cho , Jinwook Burm
Abstract: An analog-to-digital converter includes a comparator configured to compare an input voltage and a conversion voltage and to generate a comparison result; a digital-to-analog converter configured to generate the conversion voltage according to a digital output signal; and a control circuit including a conversion control circuit configured to determine the digital output signal corresponding to the input voltage based on the comparison result; and a correction control circuit configured to correct an error of the digital output signal by increasing or decreasing the digital output signal based on the comparison result after the digital output signal is determined.
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公开(公告)号：US20240396561A1
公开(公告)日：2024-11-28
申请号：US18794604
申请日：2024-08-05
Applicant: Frank R. Dropps
Inventor： Frank R. Dropps
IPC: H03M1/06 , G01K1/02 , G01K1/14 , G01K3/04 , G01K7/01 , G01K7/42 , G01K13/20 , H03M1/00 , H03M1/08 , H03M1/10 , H03M1/12 , H03M1/36
Abstract: A plurality of devices of a circuit perform a function associated with the circuit. A compensation module obtains a temperature value and/or core voltage value associated with the circuit and uses the temperature value and/or the core voltage value to adjust at least one device of the plurality of devices. The adjustment may include using one or more source resisters connected to the at least one device of the plurality of devices to adjust a device voltage threshold. The plurality of devices may perform analog to digital conversion, and the compensation module may generate a digital offset value using the temperature value and/or the core voltage value and add or subtract the digital offset value from an unadjusted digital output value to compensate for a change in the temperature value and/or the core voltage value.
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公开(公告)号：US20240388302A1
公开(公告)日：2024-11-21
申请号：US18661769
申请日：2024-05-13
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： JIAN-RU LIN , YING-CHENG WU , CHIA-WEI YU
IPC: H03M1/06
Abstract: A compensation circuit is applied to a successive-approximation register (SAR) analog-to-digital converter (ADC) (SAR ADC) that includes a comparator, and the comparator includes a first transistor and a second transistor. The first transistor and the second transistor receive an input signal during a sampling phase, and the comparator determines at least one bit of a digital output code during a comparison phase. The compensation circuit includes a voltage generator coupled to the comparator for providing a first voltage to a first bulk of the first transistor and a second bulk of the second transistor during the sampling phase and providing a second voltage to the first bulk of the first transistor and the second bulk of the second transistor during the comparison phase.
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