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公开(公告)号：US12126353B2
公开(公告)日：2024-10-22
申请号：US17945136
申请日：2022-09-15
Applicant: REALTEK SEMICONDUCTOR CORPORATION
Inventor： Wei-Cian Hong
CPC classification number: H03M1/34 , H03M1/0863 , H03M1/462 , H03M1/468
Abstract: The present invention discloses an analog-to-digital conversion circuit having quick tracking mechanism is provided. A positive and a negative capacitor arrays receive a positive and a negative input voltages and output a positive and a negative output voltages. A first and a second comparators performs comparison thereon respectively according to and not according to a reference voltage to generate a first and a second comparison results. A control circuit does not perform level-shifting when a difference between the positive and the negative output voltages is not within a predetermined range. The control circuit assigns the positive and the negative capacitor arrays a voltage up-tracking direction and a voltage down-tracking direction respectively to switch a capacitor enabling combination with digital codes according to the second comparison result, and outputs the digital codes as a digital output signal when the positive and the negative output voltages equal.
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公开(公告)号：US12047087B2
公开(公告)日：2024-07-23
申请号：US17771268
申请日：2019-10-31
Applicant: Nippon Telegraph and Telephone Corporation
Inventor： Tadashi Minotani , Kenichi Matsunaga
Abstract: An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.
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公开(公告)号：US12040807B2
公开(公告)日：2024-07-16
申请号：US17576681
申请日：2022-01-14
Applicant: Senbiosys
Inventor： Assim Boukhayma , Massimiliano Bracco , Antonino Caizzone
CPC classification number: H03M1/002 , H03M1/0634
Abstract: A cyclic analog to digital converter for digitizing an output from a photoplethysmography sensor has a buffer amplifier for setting a voltage of the feedback capacitance. Additionally, digital averaging circuit is preferably provided for averaging the digital output from the cyclic analog to digital converter for the several conversions. Finally, voting logic is additionally provided for declaring the digital bits based on successive comparisons by the one or more comparators.
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公开(公告)号：US12009828B2
公开(公告)日：2024-06-11
申请号：US18143695
申请日：2023-05-05
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/0626 , H03M1/0854 , H03M1/1245 , H03M1/34 , H03M3/462 , H03M3/476 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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公开(公告)号：US11921139B2
公开(公告)日：2024-03-05
申请号：US16655696
申请日：2019-10-17
Inventor： Jae Joon Kim , Seungmok Kim , Kyeong-Hwan Park
CPC classification number: G01R27/14 , G01R27/00 , H03F3/45179 , H03M1/34 , H03M3/04
Abstract: A differential mode converter that includes an input mode converter configured to convert an input voltage in a single-ended mode into a first differential voltage and a second differential voltage to be output, the first differential voltage and the second differential voltage being symmetric with respect to a reference voltage and having a form of a square wave; and a chopper configured to receive the first differential voltage and the second differential voltage and determine a first chopping voltage and a second chopping voltage based on the first differential voltage and the second differential voltage to output the first chopping voltage and the second chopping voltage, the first chopping voltage and the second chopping voltage being symmetric with respect to the reference voltage and having a form of a DC voltage.
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Patent Agency Ranking
公开(公告)号：US11811416B2
公开(公告)日：2023-11-07
申请号：US17550493
申请日：2021-12-14
Applicant: International Business Machines Corporation
Inventor： Kyu-hyoun Kim , Mingu Kang , Ankur Agrawal , Monodeep Kar
CPC classification number: H03M1/002
Abstract: An apparatus comprises at least one processor and at least one memory including instruction code configured to, with the at least one processor, cause the apparatus at least to perform a successive approximation analog-to-digital conversion of an analog input, representing a result of multiplication of first and second vectors, to a digital output by determining an upper bound on the result of multiplication of the first and second vectors, identifying, based at least in part on the determined upper bound, at least a portion of the successive approximation analog-to-digital conversion to be skipped, and skipping the identified portion of the successive approximation analog-to-digital conversion.
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公开(公告)号：US11804848B2
公开(公告)日：2023-10-31
申请号：US17705776
申请日：2022-03-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaehoon Lee , Yong Lim , Seunghyun Oh
CPC classification number: H03M1/466 , H03K3/356104 , H03M1/1245 , H03M1/462
Abstract: An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.
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公开(公告)号：US20230275590A1
公开(公告)日：2023-08-31
申请号：US18143695
申请日：2023-05-05
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/1245 , H03M1/0626 , H03M1/0854 , H03M1/34 , H03M3/476 , H03M3/462 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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公开(公告)号：US20230246650A1
公开(公告)日：2023-08-03
申请号：US18127400
申请日：2023-03-28
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/1245 , H03M1/0626 , H03M1/0854 , H03M1/34 , H03M3/476 , H03M3/462 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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10.发明公开公开(公告)号：US20230238970A1
公开(公告)日：2023-07-27
申请号：US18127817
申请日：2023-03-29
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/1245 , H03M1/0626 , H03M1/0854 , H03M1/34 , H03M3/476 , H03M3/462 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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