公开(公告)号：WO2010141908A1

公开(公告)日：2010-12-09

申请号：PCT/US2010/037528

申请日：2010-06-04

Applicant: QUALCOMM INCORPORATED ,  TASIC, Aleksandar M. ,  CASSIA, Marco

Inventor： TASIC, Aleksandar M. ,  CASSIA, Marco

IPC: H03F3/193 ,  H04B1/40

CPC classification number: H04B1/406 ,  H03F3/195 ,  H03F3/45179 ,  H03F3/45475 ,  H03F3/72 ,  H03F2203/45386 ,  H03F2203/45394 ,  H03F2203/7209

Abstract: A device with multiple multi-mode low-noise amplifiers (LNAs), each with common operating modes and separate operating frequency bands, are coupled to shared degenerative inductors for common operating modes. Common load inductors are coupled to the multi-mode LNA outputs to reduce the number of load inductors required. The multi-mode LNAs have parallel transistor gain stages and form part of an integrated circuit (IC) for use in a wireless communication receiver. Each multi-mode LNA has the capability to switch between at least one higher linearity transistor gain stage and at least one lower linearity transistor gain stage for different operating modes. Multiple lower linearity transistor gain stages for different multi-mode LNAs may be merged into a single lower linearity transistor gain stage shared among multiple multi-mode LNAs through multiple RF switches between a set of common RF inputs and common inputs and common input matching networks.

Abstract translation: 具有多个多模低噪声放大器（LNA）的器件，每个具有共同的工作模式和独立的工作频带，耦合到用于常见工作模式的共享退化电感器。 常见的负载电感器耦合到多模LNA输出，以减少所需的负载电感器的数量。 多模LNA具有并联晶体管增益级并且构成用于无线通信接收机的集成电路（IC）的一部分。 每个多模式LNA具有在至少一个较高线性度晶体管增益级与用于不同操作模式的至少一个较低线性度晶体管增益级之间切换的能力。 用于不同多模LNA的多个下线性晶体管增益级可以通过一组公共RF输入和公共输入和公共输入匹配网络之间的多个RF开关合并到多个多模LNA之间共享的单个下线性晶体管增益级中。

公开(公告)号：WO2010132699A1

公开(公告)日：2010-11-18

申请号：PCT/US2010/034784

申请日：2010-05-13

Applicant: QUALCOMM INCORPORATED ,  CASSIA, Marco ,  TASIC, Aleksandar M.

Inventor： CASSIA, Marco ,  TASIC, Aleksandar M.

IPC: H03F3/21 ,  H03F3/45 ,  H03F3/72 ,  H03F3/19 ,  H03G1/00

CPC classification number: H03F3/72 ,  H03F3/19 ,  H03F3/211 ,  H03F3/45183 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/429 ,  H03F2200/451 ,  H03F2203/21136 ,  H03F2203/21178 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45616 ,  H03F2203/45702 ,  H03F2203/7209 ,  H03F2203/7215 ,  H03F2203/7236 ,  H03F2203/7239

Abstract: Techniques for designing a switchable amplifier are described. In one aspect, a switchable amplifier including a core amplifier circuit configured to selectively enable one or more parallel input transistor pairs is described. The core amplifier circuit comprises a permanently enabled input transistor pair. In another aspect, a device operable between a first mode of operation and a second mode of operation comprising a receiver logic circuit for selectably enabling and disabling a plurality of input transistor pairs within a switchable amplifier is described where the switchable amplifier also includes a core amplifier circuit coupled to the receiver logic circuit for selectably enabling and disabling a transistor pair therein. The described switchable amplifiers result in the ability to provide varying amplifier performance characteristics based upon the current mode of operation of the device.

Abstract translation: 描述了用于设计可切换放大器的技术。 在一个方面，描述了一种可切换放大器，其包括被配置为选择性地启用一个或多个并行输入晶体管对的核心放大器电路。 核心放大器电路包括永久使能的输入晶体管对。 在另一方面，描述了在第一操作模式和第二操作模式之间操作的装置，其包括用于可切换地启用和禁用可切换放大器内的多个输入晶体管对的接收器逻辑电路，其中可切换放大器还包括芯放大器 耦合到接收器逻辑电路的电路，用于可选地启用和禁用其中的晶体管对。 所描述的可切换放大器导致基于设备的当前操作模式来提供变化的放大器性能特征的能力。

公开(公告)号：WO2011103103A1

公开(公告)日：2011-08-25

申请号：PCT/US2011/024942

申请日：2011-02-15

Applicant: QUALCOMM Incorporated ,  TASIC, Aleksandar M. ,  DENG, Junxiong ,  QIAO, Dongjiang

Inventor： TASIC, Aleksandar M. ,  DENG, Junxiong ,  QIAO, Dongjiang

IPC: H03K21/08 ,  H03K23/66

CPC classification number: H03K21/08 ,  H03K23/66 ,  H03L7/1976

Abstract: A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.

Abstract translation: 三分之一电路包括三个动态触发器链和组合逻辑的反馈电路。 分频电路接收时钟信号，同步地对每个动态触发器进行时钟。 反馈电路将反馈信号提供给链的第一动态触发器。 在第一模式中，来自第一触发器的从动级的信号和来自第二触发器的从动级的信号由反馈电路用于产生反馈信号。 在第二模式中，来自第一触发器的主级的信号和来自第二触发器的主级的信号由反馈电路用于产生反馈信号。 通过正确选择该模式，扩展整体分频器的频率范围。 组合逻辑将三十三％的占空比信号从触发器链转换为五十％的占空比正交信号。