公开(公告)号：WO2015157932A1

公开(公告)日：2015-10-22

申请号：PCT/CN2014/075472

申请日：2014-04-16

Applicant: INTEL CORPORATION ,  AGRAWAL, Anil ,  MUTHIYALU, Satish ,  CHEN, Yingwen ,  GANESAN, Meera

Inventor： AGRAWAL, Anil ,  MUTHIYALU, Satish ,  CHEN, Yingwen ,  GANESAN, Meera

IPC: G11C29/00

CPC classification number: G06F11/0793 ,  G06F3/0614 ,  G06F3/0652 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/106 ,  G11C29/52 ,  G11C2029/0409

Abstract: Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment.In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

Abstract translation: 用于为包括一个或多个备用存储器段的存储器的平台提供错误检测和校正的技术和机制。 在一个实施例中，存储器控制器执行包括对多个当前活动存储器段中的错误的检测的第一擦除操作。 对于一个或多个存储器段执行附加的巡检擦除，而存储器段可用于作为替换存储器段激活。在另一个实施例中，如果不可校正的错误事件是不可校正的错误事件，则发出第一​​处理程序进程（但不是第二处理程序进程） 基于活动段擦除检测到，而如果基于备用段擦除检测到不可校正的错误事件，则发送第二处理程序进程（但不是第一处理程序进程）。 在第一个处理程序进程和第二个处理程序进程中，只有第一个处理程序进程的信号会导致平台的崩溃事件。

公开(公告)号：WO2023033822A1

公开(公告)日：2023-03-09

申请号：PCT/US2021/048751

申请日：2021-09-01

Applicant: INTEL CORPORATION

Inventor： SHARMA, Manish ,  MISHRA, Vikas ,  THOMAIYAR, Richard Marian ,  BODIREDDY, Vikram ,  JAVEED, Ashraf ,  MUTHIYALU, Satish

IPC: G06F1/20 ,  G05D23/19 ,  G05B13/04 ,  G06F9/50 ,  G06F15/78

Abstract: Apparatus and methods for implementing an adaptive Dynamic Temperature Range (DTR) control mechanism to extend dynamic temperature range. A DTR control manager is provided to initiate retrain/recalibrate high-speed IO (input-output) links without link reset and extend the dynamic temperature range to the entire operating range based on thermal and other conditions. The DTR control manager ensures optimized retraining/recalibration of the link, which is based on system level parameters (like ambient temperature, fan speed, thermal zone of the devices etc.) and other environmental conditions. In some embodiments the mechanism or algorithm of the DTR control manager can be implemented in a BMC (Baseboard Management controller) or the like and hence enables the adaptive DTR solution in an operating system (OS) agnostic and seamless manner.

公开(公告)号：WO2013081616A1

公开(公告)日：2013-06-06

申请号：PCT/US2011/062788

申请日：2011-12-01

Applicant: INTEL CORPORATION ,  GUPTA, Saurabh ,  MUTHIYALU, Satish

Inventor： GUPTA, Saurabh ,  MUTHIYALU, Satish

IPC: G06F12/00 ,  G06F12/16 ,  G06F9/06

CPC classification number: G06F3/065 ,  G06F11/0724 ,  G06F11/076 ,  G06F11/1666 ,  G06F11/2017

Abstract: Method, apparatus and systems for performing hardware-based memory migration and copy operations. Under the method, a first portion of memory in a computer system accessed via a first memory controller is migrated or copied to a second portion of memory accessed via a second memory controller using a hardware-based scheme that is implemented independent of and transparent to software running on a computer system. The memory migration and/or copy operations can be used to initialize a memory mirror configuration under which data in first and second portions of memory are mirrored, and to perform memory migration operations in which data in a first portion of memory is migrated to a second portion of memory under the control of hardware in a manner in which the memory migration can be performed during run-time without a significant reduction in performance. In addition, poison data indicating failed cache lines may be migrated or copied such that data corresponding to migrated or copied poisoned cache lines are not used.

Abstract translation: 用于执行基于硬件的存储器迁移和复制操​​作的方法，装置和系统。 在该方法下，经由第一存储器控制器访问的计算机系统中的存储器的第一部分被迁移或复制到经由第二存储器控制器访问的存储器的第二部分，其使用独立于并且对软件透明地实现的基于硬件的方案 在计算机系统上运行。 存储器迁移和/或复制操作可用于初始化存储器镜像配置，在存储器镜像配置下，存储器的第一和第二部分中的数据被镜像，并且执行存储器迁移操作，其中存储器的第一部分中的数据被迁移到第二 在硬件控制下的存储器部分以可以在运行时执行存储器迁移而不显着降低性能的方式。 此外，可以迁移或复制指示失败的缓存行的毒药数据，使得不使用与迁移或复制的中毒高速缓存行相对应的数据。