公开(公告)号：WO2013109650A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021776

申请日：2013-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： SASSONE, Peter, G. ,  MAMIDI, Suman ,  ABRAHAM, Elizabeth ,  VENKUMAHANTI, Suresh, K. ,  CODRESCU, Lucian

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6026

Abstract: Systems and methods for populating a cache using a hardware prefetcher are disclosed. A method for prefetching cache entries includes determining an initial stride value based on at least a first and second demand miss address in the cache, verifying the initial stride value based on a third demand miss address in the cache, prefetching a predetermined number of cache entries based on the verified initial stride value, determining an expected next miss address in the cache based on the verified initial stride value and addresses of the prefetched cache entries; and confirming the verified initial stride value based on comparing the expected next miss address to a next demand miss address in the cache. If the verified initial stride value is confirmed, additional cache entries are prefetched. If the verified initial stride value is not confirmed, further prefetching is stalled and an alternate stride value is determined.

Abstract translation: 公开了使用硬件预取器填充高速缓存的系统和方法。 用于预取高速缓存条目的方法包括基于高速缓存中的至少第一和第二请求未命中地址来确定初始步幅值，基于高速缓存中的第三请求未命中地址来验证初始步幅值，预取数量的高速缓存条目 基于所验证的初始步幅值，基于所述经验证的初始步幅值和所述预取高速缓存条目的地址来确定所述高速缓存中的预期下一未命中地址; 并且基于将预期的下一个未命中地址与高速缓存中的下一个请求未命中地址进行比较来确认已验证的初始步幅值。 如果确认了验证的初始步幅值，则预取额外的高速缓存条目。 如果验证的初始步幅值未被确认，则进一步预取停止并且确定替代步幅值。

公开(公告)号：WO2013109651A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021777

申请日：2013-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： SASSONE, Peter, G. ,  MAMIDI, Suman ,  ABRAHAM, Elizabeth ,  VENKUMAHANTI, Suresh, K. ,  CODRESCU, Lucian

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/381 ,  G06F9/383

Abstract: Systems and methods for prefetching cache lines into a cache coupled to a processor. A hardware prefetcher is configured to recognize a memory access instruction as an autoincrement-address (AIA) memory access instruction, infer a stride value from an increment field of the AIA instruction, and prefetch lines into the cache based on the stride value. Additionally or alternatively, the hardware prefetcher is configured to recognize that prefetched cache lines are part of a hardware loop, determine a maximum loop count of the hardware loop, and a remaining loop count as a difference between the maximum loop count and a number of loop iterations that have been completed, select a number of cache lines to prefetch, and truncate an actual number of cache lines to prefetch to be less than or equal to the remaining loop count, when the remaining loop count is less than the selected number of cache lines.

Abstract translation: 将高速缓存线预取到耦合到处理器的高速缓存中的系统和方法。 硬件预取器被配置为将存储器访问指令识别为自动增量地址（AIA）存储器访问指令，从AIA指令的增量字段推断步幅值，并且基于步幅值将预取行预取到高速缓存中。 另外或替代地，硬件预取器被配置为识别预取的高速缓存行是硬件循环的一部分，确定硬件循环的最大循环计数，以及剩余循环计数作为最大循环计数和循环数之间的差 已经完成的迭代，当剩余循环数小于选定数量的缓存时，选择要预取的高速缓存行数，并将实际数量的缓存行预截取为小于或等于剩余循环计数 线。