公开(公告)号：WO1993025019A1

公开(公告)日：1993-12-09

申请号：PCT/JP1993000735

申请日：1993-06-01

Applicant: FUJITSU LIMITED ,  AONO, Yoshihito ,  IWAMATSU, Takanori ,  KAWASAKI, Toshio ,  KOBAYASHI, Kenzo

Inventor： FUJITSU LIMITED

IPC: H04J11/00

CPC classification number: H04B7/005 ,  H04B7/002 ,  H04B7/10

Abstract: This compensator comprises digital conversion means (11) for digitally converting the demodulated signals of one of the two channels formed individually by use of the carrier waves the polarizations of which are orthogonal to each other and the frequencies of which are the same; interference compensating means (13) for compensating the interference of the digitally-converted demodulated signals with the demodulated signals of the other channel; and integrating means (15) for integrating the digitally-converted demodulated signals and negatively feed back them to the digital conversion means (11).

Abstract translation: 该补偿器包括数字转换装置（11），用于通过使用其极化彼此正交并且频率相同的载波来单独形成的两个通道之一的解调信号进行数字转换; 干扰补偿装置，用于补偿数字转换的解调信号与另一个信道的解调信号的干扰; 和积分装置（15），用于对数字转换的解调信号进行积分并将其反馈给数字转换装置（11）。

公开(公告)号：WO1993017518A1

公开(公告)日：1993-09-02

申请号：PCT/JP1993000236

申请日：1993-02-25

Applicant: PFU LIMITED ,  FUJITSU LIMITED ,  KAJI, Yukio ,  NAKAJIMA, Toshiki

Inventor： PFU LIMITED ,  FUJITSU LIMITED

IPC: H04N01/40

CPC classification number: G06K9/38 ,  G06K2209/01 ,  H04N1/401 ,  H04N1/403 ,  H04N1/4076

Abstract: In a first mode of the present invention, provided is a white level setting method for an image scanner, in which this white level used for the next scanline is so set that a source document or a w white reference is scanned, the analogue image signal produced by the scanning is compared with a predetermined analogue white level signal, the digital image signal corresponding to the image on the source document is then generated, and the white level is calculated from this digital image signal. In a second mode of the present invention, provided is a binary-code judgment method for an image scanner, in which data of an image having been read is divided into blocks of a given unit, the change rate of density data of each block is found, edge portions of the image data is detected using the rate, and slice value of each block for binarizing the image data is determined on the basis of the density data.

公开(公告)号：WO1993015580A1

公开(公告)日：1993-08-05

申请号：PCT/JP1993000100

申请日：1993-01-28

Applicant: FUJITSU LIMITED ,  AWATA, Yutaka ,  KAKUISHI, Mitsuo

Inventor： FUJITSU LIMITED

IPC: H04L27/00

CPC classification number: H04Q1/50 ,  G06F1/32 ,  H04L2007/047 ,  H04Q1/30

Abstract: An input analog signal having periodicity is converted to a 1-bit digital signal by an A/D convertor (42) and is then converted to a parallel signal by a serial-parallel convertor (43). Correlation between the parallel signal and a reference signal train is calculated by a correlation device (45). When this correlationship is obtained, it is held by a hold circuit (48) and a tone signal detection result is outputted. In this way, the tone signal is detected by a simple circuit construction having low power consumption.

公开(公告)号：WO1993015505A1

公开(公告)日：1993-08-05

申请号：PCT/JP1993000110

申请日：1993-01-29

Applicant: FUJITSU LIMITED ,  SASAMOTO, Tatsuro ,  MORI, Kazunori

Inventor： FUJITSU LIMITED

IPC: G11B21/10

CPC classification number: G11B5/59688 ,  G11B5/59622

Abstract: A disk apparatus which comprises at least one disk; a head for scanning the main plane of the disk substantially in a radial direction and reproducing servo signals on the basis of a servo pattern on the main plane; a rotation mechanism for moving the head substantially in the radial direction along the main plane of the disk; an amplifier for receiving the servo signals reproduced by the head and amplifying the signals with a predetermined gain; a signal processor for separating first and second position control signals (POSN, POSQ) having the phases thereof mutually deviated by 90 DEG from the servo signal; a level detector for determining a head position, at which the first and second position control signals (POSN, POSQ) simultaneously have the same level value, and the level value at that head position; a gain controller for controlling the gain of the amplifier so that the absolute value of the level value reaches a predetermined level value; and head position control means for controlling the driving unit on the basis of the combination of the first and second position control signals (POSN, POSQ) and for setting the head to a predetermined track on the basis of the head position at which the first and second position control signals (POSN, POSQ) simultaneously have the same predetermined level value.

Abstract translation: 一种盘装置，包括至少一个盘; 用于基本上在径向上扫描盘的主平面并基于主平面上的伺服图案再现伺服信号的头部; 旋转机构，用于沿着所述盘的主平面沿径向大致移动所述头部; 放大器，用于接收头部再现的伺服信号，并以预定的增益放大信号; 信号处理器，用于分离其相位与伺服信号相互偏离90°的相位的第一和第二位置控制信号（POSN，POSQ）; 用于确定头位置的电平检测器，其中第一和第二位置控制信号（POSN，POSQ）同时具有相同的电平值，以及在该头部位置处的电平值; 增益控制器，用于控制放大器的增益，使得电平值的绝对值达到预定电平值; 以及头位置控制装置，用于根据第一和第二位置控制信号（POSN，POSQ）的组合来控制驱动单元，并且用于基于头位置将头设置到预定轨迹， 第二位置控制信号（POSN，POSQ）同时具有相同的预定电平值。

公开(公告)号：WO1993012525A1

公开(公告)日：1993-06-24

申请号：PCT/JP1992001608

申请日：1992-12-09

Applicant: FUJITSU LIMITED ,  AKAOGI, Takao ,  KAWASHIMA, Hiromi ,  TAKEGUCHI, Tetsuji ,  HAGIWARA, Ryoji ,  KASA, Yasushi ,  ITANO, Kiyoshi ,  OGAWA, Yasushige ,  KAWAMURA, Shouichi

Inventor： FUJITSU LIMITED

IPC: G11C16/06

CPC classification number: G11C29/82 ,  G05F3/205 ,  G11C5/145 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  H03K3/356147 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/215

Abstract: A flash memory improved in its erasing operation by shortening its erasing time, wherein, when data is written prior to erasing, by selecting a plurality of lines of at least either of word lines and bit lines simultaneously, data is written into a plurality of transistors in concurrence.

Abstract translation: 闪存通过缩短擦除时间来改善其擦除操作，其中当通过同时选择字线和位线中的至少一个的数行时，在擦除之前写入数据时，将数据写入多个晶体管 同意。

公开(公告)号：WO1993007580A1

公开(公告)日：1993-04-15

申请号：PCT/JP1992001277

申请日：1992-10-02

Applicant: FUJITSU LIMITED ,  KANDA, Shinji ,  WAKITANI, Jun ,  MARUYAMA, Tsugito ,  MORITA, Toshihiko

Inventor： FUJITSU LIMITED

IPC: G06F15/70

CPC classification number: G06K9/4633 ,  G06K9/4609 ,  G06T5/20 ,  G06T7/12 ,  G06T7/13 ,  G06T7/73

Abstract: A method of determining the direction of a segment of a contour in a local region of a binary profile image. The number of pixels having a predetermined value and existing in a plurality of radial directions whose center is one of the pixels in a local region having the predetermined value is determined, and the segment is judged to exist in a direction in which the number of pixels is greater. Furthermore, when the number of pixels of the predetermined value existing in a direction is greater by a predetermined value than the sum of the numbers of pixels of the predetermined value existing on both adjacent directions, the segment is judged to exist in the direction. Two directions in which the numbers of pixels are greater are detected for each pixel of the contour points. Whether these two directions are points constituting a segment or points constituting a segment in a quasi-line direction or points near a corner are determined depending on whether or not they are in a 180° direction or how much they are different from a 180° direction. Points constituting a segment, which are adjacent to each other and have the same direction, are detected as a segment. The position and direction are determined from each point near the corner, and representative values of the position and direction of the mutually adjacent points near the corner are determined.

Abstract translation: 确定二进制轮廓图像的局部区域中轮廓的段的方向的方法。 确定具有预定值并存在于其中心是具有预定值的局部区域中的像素之一的多个径向方向上的像素数量，并且该段被判断为存在于像素数目 更伟大。 此外，当存在于方向上的预定值的像素数量比存在于两个相邻方向上的预定值的像素数的总和大预定值时，判断该片段存在于该方向上。 对于轮廓点的每个像素，检测像素数较大的两个方向。 这两个方向是指构成一个段的点还是构成准线方向的点或靠近拐角的点的点根据它们是在180度方向还是与180度方向有多少来确定 。 构成彼此相邻且具有相同方向的段的点被检测为段。 从拐角附近的每个点确定位置和方向，确定角附近相邻点的位置和方向的代表值。

公开(公告)号：WO1993007502A1

公开(公告)日：1993-04-15

申请号：PCT/JP1992001289

申请日：1992-10-05

Applicant: FUJITSU LIMITED ,  SATO, Toshiro ,  YAMAMOTO, Kunitoshi ,  ADACHI, Hiroyuki

Inventor： FUJITSU LIMITED

IPC: G01R31/28

CPC classification number: G01R31/31855 ,  G01R31/317 ,  G01R31/318558 ,  G01R31/318577

Abstract: A pin scan-in system driving circuit for driving pin scan-in circuits for detecting short-circuits and breakages of the interconnections of a circuit mounting board, the driving circuit having a small number of gates. The pin scan-in system driving circuit is for driving a pin scan-in circuit disposed in an LSI logic circuit, and in the LSI logic circuit there are provided with pin scan-in circuit selection means for selecting a pin scan-in circuit, and selection-state keeping means for keeping the state selected by the pin scan-in circuit selection means.

公开(公告)号：WO1993005429A1

公开(公告)日：1993-03-18

申请号：PCT/JP1992001138

申请日：1992-09-04

Applicant: FUJITSU LIMITED ,  FUKUSHIMA, Nobuhiro

Inventor： FUJITSU LIMITED

IPC: G02B27/28

CPC classification number: G02B6/2746 ,  G02B5/3083 ,  G02B6/4209 ,  G02B27/283 ,  G02F1/093 ,  G02F2203/06

Abstract: An optical device for connecting first and second optical fibers through an optical path disposed between them, which has at least two functions including the function of an optical isolator. Parallel beams emitted from an excitation end of the first optical fiber (1) and collimated by a lens (3) pass sequentially through a birefrigence device (4), a magneto-optical device (5) and a birefrigence device (6) in order named, are converged by a lens (7) and are incident into the second optical fiber from its excitation end. However, the beam from the second optical fiber does not couple with the first optical fiber (1). The beam from an excitation port (8) couples with the first optical fiber. This optical device is suitable for an optical amplification system and a bidirectional optical transmission system.

公开(公告)号：WO1993004431A1

公开(公告)日：1993-03-04

申请号：PCT/JP1992001035

申请日：1992-08-13

Applicant: FUJITSU LIMITED ,  MORIOKA, Tetsuya

Inventor： FUJITSU LIMITED

IPC: G06F12/08

CPC classification number: G06F12/0822 ,  G06F12/1054

Abstract: A system for controlling buffer memory using a part of a page address portion of a logical address and a part of an inside-page address portion as a line address, the system being provided with a TAG1 portion (13, 17) of each of a plurality of pipelines (IF, OP) disposed inside a CPU (1) in order to retrieve hit/mistake by the use of the part of the page address portion of the logical address and the part of the inside-page address as a basic line address, a DATA portion (14, 18) for holding data when each of the TAG1 portions is retrieved and hit by the basic line address, and TAG2 portions (21, 22) disposed inside a MCU (2) in order to retrieve hit/mistake by the use of an agreement line address obtained by changing a variable portion of the basic line address when the result proves mistake by the use of the basic line address. The TAG1 unit is retrieved by the use of only the basic line address at the time of data access, and when the result proves hit, access is made to the DATA unit. When the result proves mistake, on the other hand, the TAG2 unit is retrieved by the use of the basic line address and the agreement line address. When the result provides hit at this time, nullification of the DATA unit, move-out and nullification, and if necessary, activation of move-in, are made.

Abstract translation: 一种用于使用逻辑地址的页面地址部分的一部分和内部页面地址部分的一部分作为行地址来控制缓冲存储器的系统，该系统被提供有一个TAG1部分（13,17） 多个管道（IF，OP）设置在CPU（1）内，以便通过使用逻辑地址的页面地址部分的一部分和内部页面地址的一部分作为基本行来检索命中/错误 地址，用于当每个TAG1部分被基本行地址检索和命中时保存数据的DATA部分（14,18）以及设置在MCU（2）内的TAG2部分（21,22），以便检索命中/ 通过使用通过使用基本行地址来证明错误的基本行地址的可变部分而获得的协议行地址的错误。 通过在数据访问时仅使用基本行地址来检索TAG1单元，并且当结果被命中时，对DATA单元进行访问。 另一方面，当结果证明错误时，通过使用基本行地址和协议行地址来检索TAG2单元。 当结果在此时提供命中时，数据单元的无效，移出和无效，并且如果需要，进行移入的激活。

公开(公告)号：WO1993002485A1

公开(公告)日：1993-02-04

申请号：PCT/JP1992000913

申请日：1992-07-17

Applicant: FUJITSU LIMITED ,  TOZAWA, Norio

Inventor： FUJITSU LIMITED

IPC: H01P03/08

CPC classification number: H01P3/081 ,  H05K1/0237 ,  H05K1/0265 ,  H05K3/244 ,  H05K3/4015 ,  H05K2201/098 ,  H05K2201/1028

Abstract: A microstrip line capable of feeding a large DC current, in spite of maintaining a high characteristic impedance. The microstrip line is provided with a dielectric base (10), an earthing conductor (12), a conductor strip (14), and an upper conductor part (16). The upper conductor part (16) is provided nearly on the central line of the conductor strip (14), and has a section which is thick in a vertical direction and whose width w1 of the lower base (16a) is narrower than the width W of the conductor strip (14) and respective width w2 from the base (16a) to its opposite side (16b) are nearly equal to the width w1 of the base (16a) or become larger than the width w1 at upper parts. The upper conductor part (16) of such sectional shape is formed by welding onto the conductor strip (14) a linear member made of gold, silver or copper whose section is shaped so through etching, or by depositing on the conductor strip (14) gold, silver or copper through plating.

Abstract translation: 尽管维持高的特性阻抗，但是能够馈送大直流电流的微带线。 微带线设置有电介质基底（10），接地导体（12），导体条（14）和上导体部分（16）。 上导体部（16）大致设置在导体条（14）的中心线上，具有在垂直方向上较厚的部分，下基板（16a）的宽度w1比宽度W窄 的导体条（14）的宽度w2和从基部（16a）到其相对侧（16b）的宽度w2几乎等于基部（16a）的宽度w1或变得大于上部的宽度w1。 这种截面形状的上导体部分（16）通过在导体条（14）上焊接由金，银或铜制成的线状部件形成，其截面通过蚀刻成形，或通过沉积在导体条（14）上而形成， 金，银或铜通过电镀。