公开(公告)号：WO2014207570A3

公开(公告)日：2015-07-02

申请号：PCT/IB2014002123

申请日：2014-06-06

Applicant: MARVELL WORLD TRADE LTD

Inventor： WEN XINGZHI ,  HONG YU ,  ZHU HEFEI ,  TIAN QUNZHAO ,  CAI JEANNE Q ,  GUO SHAORI

IPC: G06F12/00

CPC classification number: G06F12/123 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0875 ,  G06F12/121 ,  G06F2212/1008 ,  G06F2212/2146 ,  G06F2212/608

Abstract: Systems and methods are provided for cache management. An example system includes a cache and a cache-management component. The cache includes a plurality of cache lines corresponding to a plurality of device endpoints, a device endpoint including a portion of a universal -serial-bus (USB) device. The cache-management component is configured to receive first transfer request blocks (TRBs) for data transfer involving a first device endpoint and determine whether a cache line in the cache is assigned to the first device endpoint. The cache-management component is further configured to, in response to no cache line in the cache being assigned to the first device endpoint, determine whether the cache includes an empty cache line that contains no valid TRBs, and in response to the cache including an empty cache line, assign the empty cache line to the first device endpoint and store the first TRBs to the empty cache line.

Abstract translation: 为缓存管理提供了系统和方法。 示例系统包括高速缓存和高速缓存管理组件。 高速缓存包括对应于多个设备端点的多个高速缓存行，包括通用 - 串行总线（USB）设备的一部分的设备端点。 高速缓存管理组件被配置为接收用于涉及第一设备端点的数据传输的第一传输请求块（TRB），并且确定高速缓存中的高速缓存行是否被分配给第一设备端点。 高速缓存管理组件还被配置为响应于高速缓存中没有分配给第一设备端点的高速缓存行，确定高速缓存是否包括不包含有效TRB的空高速缓存行，并且响应于高速缓存包括 空的缓存行，将空的缓存行分配给第一个设备端点，并将第一个TRB存储到空的高速缓存行。

公开(公告)号：WO2014164328A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/021922

申请日：2014-03-07

Applicant: CLOUD PHYSICS, INC.

Inventor： WALDSPURGER, Carl A. ,  PARK, Nohhyun

IPC: G06F12/08

CPC classification number: G06F12/1063 ,  G06F11/3447 ,  G06F11/3457 ,  G06F12/0802 ,  G06F12/109 ,  G06F12/123 ,  G06F17/5022 ,  G06F2201/885 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  G06F2212/684

Abstract: Cache utility curves are determined for different software entities depending on how frequently their storage access requests lead to cache hits or cache misses. Although possible, not all access requests need be tested, but rather only a subset, determined by whether a hash value of each current storage location identifier (such as an address or block number) meets one or more sampling criteria.

Abstract translation: 根据存储访问请求导致缓存命中或高速缓存未命中的频率，为不同的软件实体确定高速缓存实用程序曲线。 虽然可能，但并不是所有的访问请求都需要被测试，而只是一个子集，由每个当前的存储位置标识符（例如地址或块号）的哈希值是否满足一个或多个采样标准来确定。

公开(公告)号：WO2014076504A1

公开(公告)日：2014-05-22

申请号：PCT/GB2013/053042

申请日：2013-11-18

Applicant: SMARTFOCUS HOLDINGS LIMITED

Inventor： CREAMER, Paul ,  WELLS, Charles

IPC: G06F17/30

CPC classification number: G06F12/122 ,  G06F12/08 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/0888 ,  G06F12/12 ,  G06F12/121 ,  G06F12/123 ,  G06F17/3048

Abstract: A database cache manager for controlling a composition of a plurality of cache entries in a data cache is described. Each cache entry is a result of a query carried out on a database of data records, the cache manager being arranged to remove cache entries from the cache based on a cost of removal factor which is comprised of a time cost,the time cost being calculated from the amount of time taken to obtain a query result to which that cache entry is related.

Abstract translation: 描述了用于控制数据高速缓存中的多个高速缓存条目的组合的数据库高速缓存管理器。 每个缓存条目是在数据记录数据库上执行的查询的结果，缓存管理器被安排为基于由时间成本，计算时间成本组成的去除因子的成本从高速缓存中移除高速缓存条目 从获取与该缓存条目相关的查询结果所花费的时间。

公开(公告)号：WO2014062616A1

公开(公告)日：2014-04-24

申请号：PCT/US2013/064940

申请日：2013-10-15

Applicant: VMWARE, INC.

Inventor： LIU, Deng ,  SCALES, Daniel J.

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0866 ,  G06F12/0897 ,  G06F12/121 ,  G06F12/123 ,  G06F12/126

Abstract: A technique for efficient cache management demotes a unit of data from a higher cache level to a lower cache level in a cache hierarchy when the higher level cache evicts the unit of data. In a virtualization computing environment, eviction of the unit of data may be inferred by observing privileged memory and disk operations performed by a guest operating system and trapped by virtualization software for execution. When the unit of data is inferred to be evicted, the unit of data is demoted by transferring the unit of data into the lower cache level. This technique enables exclusive caching without direct involvement or modification of the guest operating system. In alternative embodiments, a pseudo-driver installed within the guest operating system explicitly tracks memory operations and transmits page eviction information to the lower level cache, which is able to cache evicted pages while maintaining cache exclusivity.

Abstract translation: 当高级缓存驱逐数据单元时，用于高效缓存管理的技术将高速缓存级别的数据单元降级到高速缓存层级中的较低高速缓存级别。 在虚拟化计算环境中，可以通过观察由客户操作系统执行的特权存储器和磁盘操作并被虚拟化软件捕获以执行来推断数据单元的驱逐。 当推断数据单位被驱逐时，通过将数据单元传送到较低的缓存级别来降低数据单位。 这种技术可以独立的缓存，而不需要直接参与或修改客户机操作系统。 在替代实施例中，安装在客户机操作系统内的伪驱动程序显式地跟踪存储器操作，并将页面驱逐信息发送到下级缓存，其能够缓存被驱逐的页面，同时保持高速缓存独占性。

公开(公告)号：WO2014000300A1

公开(公告)日：2014-01-03

申请号：PCT/CN2012/077991

申请日：2012-06-30

Applicant: 华为技术有限公司 ,  黄剑敏 ,  宋铜铃 ,  周建军

Inventor： 黄剑敏 ,  宋铜铃 ,  周建军

IPC: G06F12/08 ,  G06F1/30

CPC classification number: G06F12/0246 ,  G06F11/1441 ,  G06F12/0804 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/122 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/1041 ,  G06F2212/225 ,  G06F2212/313 ,  G06F2212/6026

Abstract: 本发明实施例公开了一种数据缓存装置、数据存储系统及方法，其中的所述数据缓存装置通过数据接口与数据处理设备相连，所述数据缓存装置包括：控制器，与所述控制器相连的内存；所述内存用于缓存与本数据缓存装置相连的硬盘中的热点数据，所述控制器用于根据所述数据处理设备的数据读写请求向所述内存读写数据。采用本发明，不仅可以有效地提升数据的读写性能，还可以避免系统资源的浪费。

公开(公告)号：WO2013166599A1

公开(公告)日：2013-11-14

申请号：PCT/CA2013/050349

申请日：2013-05-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM CANADA LIMITED-IBM CANADA LIMITEE

Inventor： HYDE, Joseph Smith ,  ROY, Sunhojit

IPC: G06F12/02

CPC classification number: G06F12/122 ,  G06F12/123

Abstract: For a cache in which a plurality of frequently accessed data segments are temporarily stored, reference count information of the plurality of data segments, in conjunction with least recently used (LRU) information, is used to determine a length of time to retain the plurality of data segments in the cache according to a predetermined weight, where notwithstanding the LRU information, those of the plurality of data segments having a higher reference counts are retained longer than those having lower reference counts.

Abstract translation: 对于其中临时存储多个经常访问的数据段的高速缓存，多个数据段的参考计数信息结合最近最近使用的（LRU）信息被用于确定保持多个数据段的时间长度 根据预定权重的高速缓存中的数据段，尽管有LRU信息，具有较高参考计数的多个数据段中的数据段比具有较低参考计数的数据段保留更长。

公开(公告)号：WO2013095537A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066973

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  COLEMAN, James, A. ,  SRIVASTAVA, Durgesh

Inventor： COLEMAN, James, A. ,  SRIVASTAVA, Durgesh

IPC: G06F12/08 ,  G06F13/16 ,  G06F9/44

CPC classification number: G06F12/123 ,  G06F12/126 ,  G06F2212/70

Abstract: A processor device has a cache, and a cache controller that manages the replacement of a number of cache lines in the cache, in accordance with a replacement policy. A storage location is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region. Upon a cache miss of an address that lies in the real time region, the cache controller responds by loading content at the address into a cache line, and then prevents the cache line from aging as would a cache line that is in the cacheable region. Other embodiments are also described and claimed.

Abstract translation: 处理器设备具有缓存，以及高速缓存控制器，其根据替换策略来管理高速缓存中的多个高速缓存行的替换。 存储位置将被配置为定义具有可缓存区域，不可缓存区域和实时区域的存储器映射。 当位于实时区域的地址的高速缓存未命中时，高速缓存控制器通过将地址处的内容加载到高速缓存行中来响应，然后防止高速缓存行老化，如可缓存区域中的高速缓存行那样。 还描述和要求保护其他实施例。

公开(公告)号：WO2010132655A2

公开(公告)日：2010-11-18

申请号：PCT/US2010/034697

申请日：2010-05-13

Applicant: ORACLE AMERICA, INC. ,  KAPIL, Sanjiv ,  HETHERINGTON, Ricky, C.

Inventor： KAPIL, Sanjiv ,  HETHERINGTON, Ricky, C.

IPC: G06F12/08

CPC classification number: G06F12/08 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/205 ,  G06F2212/683 ,  G06F2212/7203

Abstract: System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region.

Abstract translation: 在内存层次结构中使用闪存的系统和方法。 计算机系统包括经由存储器控制器耦合到存储器层级的处理器。 存储器层级包括高速缓冲存储器，经由第一缓冲器耦合到存储器控制器的随机存取存储器的第一存储器区域以及经由闪存控制器耦合到存储器控制器的闪存的辅助存储器区域。 第一缓冲器和闪存控制器通过单个接口耦合到存储器控制器。 存储器控制器接收访问第一存储器区域中的特定页面的请求。 处理器检测与该请求相对应的页面错误，并且作为响应，使对应于特定页面的高速缓冲存储器中的高速缓存行无效，刷新无效高速缓存行，并将页面从辅助存储器区域交换到第一存储器区域。

公开(公告)号：WO2010113203A1

公开(公告)日：2010-10-07

申请号：PCT/JP2009/001453

申请日：2009-03-30

Applicant: HITACHI, LTD. ,  TAKADA, Masanori ,  NAKAMURA, Shuji ,  SHIMADA, Kentaro

Inventor： TAKADA, Masanori ,  NAKAMURA, Shuji ,  SHIMADA, Kentaro

IPC: G06F11/34 ,  G06F12/08

CPC classification number: G06F11/3447 ,  G06F11/3471 ,  G06F12/0802 ,  G06F12/123 ,  G06F2201/815 ,  G06F2201/88 ,  G06F2201/885

Abstract: The present invention obtains with high precision, in a storage system, the effect of additional installation or removal of cache memory, that is, the change of the cache hit rate and the performance of the storage system at that time. For achieving this, when executing normal cache control in the operational environment of the storage system, the cache hit rate when the cache memory capacity has changed is also obtained. Furthermore, with reference to the obtained cache hit rate, the peak performance of the storage system is obtained. Furthermore, with reference to the target performance, the cache memory and the number of disks and other resources that are additionally required are obtained.

Abstract translation: 本发明在存储系统中高精度地获得附加安装或移除高速缓冲存储器的效果，即高速缓存命中率的改变和存储系统的性能。 为了实现这一点，当在存储系统的操作环境中执行正常的高速缓存控制时，也获得高速缓存存储器容量已经改变时的高速缓存命中率。 此外，参考获得的高速缓存命中率，获得存储系统的峰值性能。 此外，参考目标性能，获得高速缓冲存储器以及另外需要的磁盘和其他资源的数量。

公开(公告)号：WO2010055030A1

公开(公告)日：2010-05-20

申请号：PCT/EP2009/064893

申请日：2009-11-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STRUMPEN, Volker ,  FRIGO, Matteo

Inventor： STRUMPEN, Volker ,  FRIGO, Matteo

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0811 ,  G06F3/0689 ,  G06F12/0897 ,  G06F12/123 ,  G06F2212/271

Abstract: A tiled storage array provides reduction in access latency for frequently-accessed values by re-organizing to always move a requested value to a front-most storage element of array. The previous occupant of the front-most location is moved backward according to a systolic pulse, and the new occupant is moved forward according to the systolic pulse, preserving the uniqueness of the stored values within the array, and providing for multiple in-flight access requests within the array. The placement heuristic that moves the values according to the systolic pulse can be implemented by control logic within identical tiles, so that the placement heuristic moves the values according to the position of the tiles within the array. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the array.

Abstract translation: 平铺的存储阵列通过重新组织来提供频繁访问值的访问延迟，从而始终将请求的值移动到阵列的最前面的存储元素。 根据收缩期脉搏，最前面的位置的前乘客向后移动，并且根据收缩脉冲向前移动新乘客，保持阵列内存储的值的唯一性，并提供多个飞行中访问 数组内的请求。 根据收缩期脉冲移动值的放置启发式可以由相同瓦片内的控制逻辑实现，使得放置启发式根据阵列内的瓦片的位置来移动值。 值的移动可以仅通过阵列内的相邻瓦片的下一个相邻连接来执行。