公开(公告)号：WO2013048525A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054480

申请日：2011-10-01

Applicant: INTEL CORPORATION ,  CHANDRASHEKAR, Kailash ,  PELLERANO, Stefano

Inventor： CHANDRASHEKAR, Kailash ,  PELLERANO, Stefano

IPC: H03K21/00 ,  H03K23/00

CPC classification number: H03K21/023 ,  H03K21/026 ,  H03K23/542

Abstract: A digital fractional frequency divider for fractionally dividing a digital frequency signal can include a plurality of clock division counter modules, a plurality of sampling modules, and a summing module. The plurality of clock division counter modules can each receive an input clock signal that is phase-shifted from a remaining plurality of input clock signals. Each clock division counter module can generate a long periodic pulse from the received input clock signal. Each sampling module can couple to an output of one of the plurality of clock division counter modules and can generate a short periodic pulse from the long periodic pulse. The summing module can sum the plurality of short periodic pulses to generate a fractional frequency clock signal.

Abstract translation: 用于分数数字频率信号的数字分数分频器可以包括多个时钟分配计数器模块，多个采样模块和求和模块。 多个时钟分配计数器模块可以各自接收从剩余的多个输入时钟信号中相移的输入时钟信号。 每个时钟分配计数器模块可以从接收到的输入时钟信号产生长周期脉冲。 每个采样模块可以耦合到多个时钟分配计数器模块中的一个的输出，并且可以从长周期脉冲产生短周期脉冲。 求和模块可以对多个短周期脉冲求和以产生分数频率时钟信号。