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    GATE DRIVE ADAPTER
    51.
    发明申请
    GATE DRIVE ADAPTER 审中-公开

    公开(公告)号：WO2019209960A1

    公开(公告)日：2019-10-31

    申请号：PCT/US2019/028926

    申请日：2019-04-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： GONG, Xun ,  FRANK, Ingolf

    IPC: H02M3/22

    Abstract: A gate drive adapter circuit (104) includes an input circuit (116), an output circuit (118), and a charge pump circuit (120). The input circuit (116) is configured to receive pulses suitable for controlling a silicon power transistor. The output circuit (118) is coupled to the input circuit (116). The output circuit (118) is configured to translate the pulses to voltages suitable for controlling a silicon-carbide power transistor. The charge pump circuit (120) is coupled to the input circuit (116) and to the output circuit (120). The charge pump circuit (120) is configured to generate a negative voltage. The output circuit (118) is configured to apply the negative voltage to translate the pulses.

    DIGITAL BUS ACTIVITY MONITOR
    52.
    发明申请
    DIGITAL BUS ACTIVITY MONITOR 审中-公开

    公开(公告)号：WO2019090007A1

    公开(公告)日：2019-05-09

    申请号：PCT/US2018/058825

    申请日：2018-11-02

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： CHARD, Gary, Franklin ,  KOH, Tpinn, Ronnie ,  SHAH, Harshil, Atulkumar

    IPC: G06F13/00 ,  G06F13/38

    Abstract: In one example, a device includes an activity monitor (130). The activity monitor (130) includes a bus interface (140) having inputs coupled to receive signals from a bus (135) and having outputs coupled to provide signals to an other device (110). The activity monitor (130) monitors the bus (135) for a message directed to a predefined address that is associated with the other device (110), in response to detecting that the other device (110) is a low power sleep mode. Also, the activity monitor (130) outputs the predefined address to the other device (110) for enabling the other device (110) to capture the predefined address, via the bus interface (140), in response to the monitored address matching the predefined address.

    TRANSISTORS HAVING GATES WITH A LIFT-UP REGION
    53.
    发明申请
    TRANSISTORS HAVING GATES WITH A LIFT-UP REGION 审中-公开

    公开(公告)号：WO2019079610A1

    公开(公告)日：2019-04-25

    申请号：PCT/US2018/056533

    申请日：2018-10-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： CAI, Jun

    IPC: H01L21/336

    Abstract: In at least one example, a transistor (100) includes a semiconductor (102), a first drift layer (112), a drain region (116), a body region (128), a source region (134), a shallow trench isolation region (114), a dielectric (119), and a gate (120). The first drift layer (112) is formed in the semiconductor (102) and has majority carriers of a first type. The drain region (116) is formed in the first drift layer (112) and has majority carriers of the first type. The body region (128) is formed in the semiconductor (102) and has majority carriers of a second type. The source region (134) is formed in the body region (128) and has majority carriers of the first type. The shallow trench isolation region (114) is formed in the first drift layer (112) and disposed between the drain region (116) and the body region (128). The dielectric (119) is formed on the semiconductor (102), and the gate (120) is formed over the dielectric (119) and has a lift-up region (122).

    ALLOY DIFFUSION BARRIER LAYER
    54.
    发明申请
    ALLOY DIFFUSION BARRIER LAYER 审中-公开

    公开(公告)号：WO2019060496A1

    公开(公告)日：2019-03-28

    申请号：PCT/US2018/051874

    申请日：2018-09-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： DADVAND, Nazlia ,  PAVONE, Salvatore Frank ,  MANACK, Christopher Daniel

    IPC: H01L23/488

    Abstract: A microelectronic device (100) includes a reflow structure (110). The reflow structure (110) has a copper-containing member (114) and a solder member (118), and a barrier layer (116) between them. The barrier layer (116) has metal grains (120), with a diffusion barrier filler (122) between the metal grains (120). The metal grains (120) include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler (122) includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler (122) is higher than in the metal grains (120) to provide a desired resistance to diffusion of copper. The barrier layer (116) includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum.

    MEETING SETUP/HOLD TIMES FOR A REPETITIVE SIGNAL RELATIVE TO A CLOCK
    57.
    发明申请
    MEETING SETUP/HOLD TIMES FOR A REPETITIVE SIGNAL RELATIVE TO A CLOCK 审中-公开

    公开(公告)号：WO2018161083A1

    公开(公告)日：2018-09-07

    申请号：PCT/US2018/020940

    申请日：2018-03-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： KRAMER, Paul, Joseph ,  CHILDS, Matthew, Hansen ,  TAFT, Robert, Callaghan

    IPC: H03K5/135

    Abstract: In described examples, clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock (100) with active and inactive clock edges (101, 102) within a clock period (T CLOCK ), and signal capture circuitry to capture repetitive signal transitions (20, 21/22) at an active clock edge, based on predefined setup and hold times (t SETUP /t HOLD ) which determine a setup/hold window (13). Clock phase adjustment circuitry is configured to adjust clock phase, so that the repetitive signal transitions (20, 21) occur within a signal capture window (14) between setup/hold windows (13). Clock phase adjustment can be based on: aligning the clock inactive edges (102) to the repetitive signal transitions (21); and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to SYSREF timing reference control signal.

    CURRENT SOURCE NOISE CANCELLATION
    58.
    发明申请
    CURRENT SOURCE NOISE CANCELLATION 审中-公开

    公开(公告)号：WO2018126159A1

    公开(公告)日：2018-07-05

    申请号：PCT/US2017/068992

    申请日：2017-12-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： VENKATARAMAN, Jagannathan ,  MIGLANI, Eeshan

    IPC: H03M1/08

    Abstract: At least some embodiments are directed to a system (100) that comprises a differential switch network (103) comprising first and second output nodes (126, 128), first and second transistors (110, 116) coupled to the network (103), and first and second resistors (108, 114) coupled to the first and second transistors (110, 116). The DAC (100) also comprises a voltage source (106) coupled to the first resistor (108) and a ground connection (112) coupled to the second resistor (114). The DAC (100) further includes a capacitor (132) coupled to the first and second transistors (110, 116) and to the second resistor (114).

    LLC RESONANT CONVERTER WITH INTEGRATED MAGNETICS
    60.
    发明申请
    LLC RESONANT CONVERTER WITH INTEGRATED MAGNETICS 审中-公开
    LLC谐振转换器与集成磁力

    公开(公告)号：WO2018089771A1

    公开(公告)日：2018-05-17

    申请号：PCT/US2017/061071

    申请日：2017-11-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

    Inventor： CHEN, Runruo

    IPC: H02M3/335 ,  H01F27/00

    Abstract: Described examples include integrated magnetic circuits for LLC resonant converters (100), including an inductor cell (122-5) and multiple transformer cells (122-1) with cores (110-1) arranged in a stack structure (130). The individual transformer cells (122-1) include primary and secondary windings (PI, SI) extending around the transformer core structure (110-1), and a secondary transistor (SRI) connected in series with the secondary winding (SI). One or more windings are shaped near core stack gaps to reduce core and winding losses. The inductor cell (122-5) includes an inductor winding (LW) extending around the inductor core structure (110-5) to provide an inductor (LR), and a capacitor (CR). The inductor cell (122-5) is arranged in the stack structure (130) with the transformer cells (122-1) to magnetically couple the transformer primary windings (PI), the inductor winding (LW) and the transformer secondary windings (SI) in a single magnetic circuit to cancel cell to cell flux.

    Abstract translation: 所描述的示例包括用于LLC谐振转换器（100）的集成磁路，包括电感器单元（122-5）和多个变压器单元（122-1），所述多个变压器单元（122-1）具有布置在 堆叠结构（130）。 各个变压器单元（122-1）包括围绕变压器铁芯结构（110-1）延伸的初级和次级绕组（PI，SI）以及与次级绕组（SI）串联连接的次级晶体管（SRI）。 一个或多个绕组在铁心堆叠间隙附近成形以减少铁心和绕组损耗。 电感器单元（122-5）包括围绕电感器芯结构（110-5）延伸以提供电感器（LR）和电容器（CR）的电感器绕组（LW）。 电感器单元（122-5）与变压器单元（122-1）一起布置在堆叠结构（130）中以将变压器初级绕组（PI），电感器绕组（LW）和变压器次级绕组（SI） ）在一个单一的磁路中消除细胞间通量。

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