公开(公告)号：WO2022216528A1

公开(公告)日：2022-10-13

申请号：PCT/US2022/022924

申请日：2022-03-31

Applicant: NVIDIA CORPORATION

Inventor： RADHAKRISHNAN, Subhashree ,  AGHDASI, Farzin

IPC: G06V10/764 ,  G06V20/58

Abstract: Apparatuses, systems, and techniques to perform action recognition. In at least one embodiment, action recognition is performed using one or more neural networks and hardware accelerators, in which the one or more neural networks are processed based on, for example, one or more quantization and pruning processes.

公开(公告)号：WO2023059748A1

公开(公告)日：2023-04-13

申请号：PCT/US2022/045820

申请日：2022-10-05

Applicant: NVIDIA CORPORATION

Inventor： CIOLKOSZ, Piotr ,  PERELYGIN, Kyrylo ,  EDWARDS, Harold Carter ,  MAXEY, Wesley

IPC: G06F9/50 ,  G06F9/5044 ,  G06F9/5061 ,  G06F9/541

Abstract: Apparatuses, systems, and techniques to perform parallel processing. In at least one embodiment, a parallel processing algorithm for performing an additive prefix scan is selected from a plurality of alternatives based on an arrangement of a group of threads provided to perform the scan.

公开(公告)号：WO2023018555A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/038739

申请日：2022-07-28

Applicant: NVIDIA CORPORATION

Inventor： MYRONENKO, Andriy ,  XU, Ziyue ,  YANG, Dong ,  ROTH, Holger ,  XU, Daguang

IPC: G06V10/82 ,  G06V20/69 ,  G06V2201/03

Abstract: Apparatuses, systems, and techniques are presented to classify objects in images. In at least one embodiment, one or more neural networks are used to identify one or more objects in one or more full images based, at least in part, on the one or more neural networks having been trained using the one or more full images and one or more portions of the one or more full images.

公开(公告)号：WO2023044353A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/076442

申请日：2022-09-14

Applicant: NVIDIA CORPORATION

Inventor： CIOLKOSZ, Piotr ,  PERELYGIN, Kyrylo ,  EDWARDS, Harold Carter ,  MAXEY, Wesley

IPC: G06F9/38

Abstract: Apparatuses, systems, and techniques to facilitate parallel processing. In at least one embodiment, an application programming interface allows a user to define a plurality of cooperative thread groups, and launch multiple cooperative thread groups in parallel provided sufficient processing resources are available.

公开(公告)号：WO2023018556A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/038741

申请日：2022-07-28

Applicant: NVIDIA CORPORATION

Inventor： SHEN, Maying ,  MOLCHANOV, Pavlo ,  YIN, Hongxu ,  MAO, Lei ,  LIU, Jianna ,  LOPEZ, Jose Manuel Alvarez

IPC: G06N3/04 ,  G06N3/08

Abstract: Apparatuses, systems, and techniques are presented to simplify neural networks. In at least one embodiment, one or more portions of one or more neural networks are cause to be removed based, at least in part, on one or more performance metrics of the one or more neural networks.

公开(公告)号：WO2023004030A1

公开(公告)日：2023-01-26

申请号：PCT/US2022/037852

申请日：2022-07-21

Applicant: NVIDIA CORPORATION

Inventor： LIU, Ming-Yu ,  NAGANO, Koki ,  SEOL, Yeongho ,  VALLE GOMES DA COSTA, Jose, Rafael ,  SEO, Jaewoo ,  WANG, Ting-Chun ,  MALLYA, Arun ,  KHAMIS, Sameh ,  PING, Wei ,  BADLANI, Rohan ,  SHIH, Kevin, Jonathan ,  CATANZARO, Bryan ,  YUEN, Simon ,  KAUTZ, Jan

IPC: G10L21/10 ,  G06N3/02 ,  G10L25/30

Abstract: Apparatuses, systems, and techniques are presented to generate media content. In at least one embodiment, a first neural network is used to generate first video information based, at least in part, upon voice information corresponding to one or more users, and a second neural network is used to generate second video information corresponding to the one or more users based, at least in part, upon the first video information and one or more images corresponding to the one or more users.

公开(公告)号：WO2022035787A1

公开(公告)日：2022-02-17

申请号：PCT/US2021/045279

申请日：2021-08-09

Applicant: NVIDIA CORPORATION

Inventor： CHOI, Jiwoong ,  ALVAREZ LOPEZ, Jose Manuel

IPC: G06K9/32 ,  G06K9/62

Abstract: Apparatuses, systems, and techniques to identify one or more objects in one or more images. In at least one embodiment, one or more objects are identified in one or more images based, at least in part, on a likelihood that one or more objects is different from other objects in one or more images.

公开(公告)号：WO2023287911A1

公开(公告)日：2023-01-19

申请号：PCT/US2022/037005

申请日：2022-07-13

Applicant: NVIDIA CORPORATION

Inventor： XU, Ziyue ,  MYRONENKO, Andriy ,  YANG, Dong ,  ROTH, Holger, Reinhard ,  ZHAO, Can ,  WANG, Xiaosong ,  XU, Daguang

IPC: G06V10/44 ,  G06V10/82

Abstract: Apparatuses, systems, and techniques are presented to predict annotations for objects in images. In at least one embodiment, boundaries of an object within an image can be identified based, at least in part, on a user-generated outline of only a portion of this object or information about a size of this object provided by a user.

公开(公告)号：WO2022241168A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/029075

申请日：2022-05-12

Applicant: NVIDIA CORPORATION

Inventor： SHIN, Jaewook ,  ATUKURI, Balaji Krishna Yugandhar ,  GORNISH, Edward H. ,  VENKATESH, Jayashree

IPC: G06F9/30 ,  G06F7/544 ,  G06F8/41 ,  G06F17/16 ,  G06F7/5443 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30192 ,  G06F9/3836 ,  G06F9/541 ,  G06F9/544 ,  G06F9/547 ,  H03M7/702

Abstract: Apparatuses, systems, and techniques to perform an operation to indicate one or more non-zero values within one or more matrices of data; to perform an API to compress one or more matrices of data; to perform a matrix multiply accumulate (MMA) operation on two or more matrices of data, wherein at least one of the two or more matrices contain compressed data; and/or to perform an API to decompress one or more matrices of data. In at least one embodiment, one or more circuits are configured to receive and compile one or more instructions to perform computational operations for a sparse matrix multiplication.

公开(公告)号：WO2023064814A1

公开(公告)日：2023-04-20

申请号：PCT/US2022/077975

申请日：2022-10-12

Applicant: NVIDIA CORPORATION

Inventor： MARATHE, Jaydeep ,  MURPHY, Michael ,  ZHANG, Xiaohua

IPC: G06F8/41 ,  G06F8/54

Abstract: Apparatuses, systems, and techniques to generate code to be performed by one or more first processors based, at least in part, on one or more indications of data to be used by one or more second processors. In at least one embodiment, a CUDA program includes host 5 code and device code, and a linker uses references for code elements in host code to link or prune code elements from device code.