公开(公告)号：WO2013006363A2

公开(公告)日：2013-01-10

申请号：PCT/US2012/044581

申请日：2012-06-28

Applicant: MICRON TECHNOLOGY, INC. ,  SILLS, Scott E.

Inventor： SILLS, Scott E.

CPC classification number: H01L45/1273 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

Abstract: The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.

Abstract translation: 本公开内容包括存储单元结构及其形成方法。 一个这样的存储单元包括相对于第一电极的底表面具有小于90度的侧壁的第一电极，包括第二电极的电极接触部分的第二电极，具有相对于 第一电极的底表面，其中第二电极在第一电极之上，以及存储元件，位于第一电极和第二电极的电极接触部分之间。

公开(公告)号：WO2013006363A3

公开(公告)日：2013-04-18

申请号：PCT/US2012044581

申请日：2012-06-28

Applicant: MICRON TECHNOLOGY INC ,  SILLS SCOTT E

Inventor： SILLS SCOTT E

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/1273 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616

Abstract: The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode.

Abstract translation: 本发明包含存储器单元结构及其形成方法。 一个这样的存储器单元包括具有相对于第一电极的底表面倾斜小于90度的侧壁的第一电极，包括第二电极的电极接触部分的第二电极，第二电极具有相对于第一电极小于90度的角度 第一电极的底表面，其中第二电极在第一电极上方，以及在第一电极与第二电极的电极接触部分之间的存储元件。

公开(公告)号：WO2013022560A2

公开(公告)日：2013-02-14

申请号：PCT/US2012/046913

申请日：2012-07-16

Applicant: MICRON TECHNOLOGY, INC. ,  SILLS, Scott E.

Inventor： SILLS, Scott E.

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/1253 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/143 ,  H01L45/146

Abstract: Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.

Abstract translation: 一些实施例包括存储器单元。 存储器单元可以包含在一对电极之间的开关区域和离子源区域。 开关区域可以被配置为可逆地保持导电桥，其中当导电桥保持在开关区内时存储单元处于低电阻状态并且当导电桥不在开关区内时处于高电阻状态 。 存储器单元可以包含跨开关区域延伸的有序框架，以将导电桥板定向在开关区域内，其中框架在存​​储器单元的高电阻状态和低电阻状态两者中保持在开关区域内。

公开(公告)号：WO2012141898A2

公开(公告)日：2012-10-18

申请号：PCT/US2012/031004

申请日：2012-03-28

Applicant: MICRON TECHNOLOGY, INC. ,  SILLS, Scott E. ,  SANDHU, Gurtej

Inventor： SILLS, Scott E. ,  SANDHU, Gurtej

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: This disclosure provides embodiments for the formation of vertical memory cell structures (38) that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line (22) height (?WL) and/or word line (22) interface surface (50) characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer (44) of an RRAM memory cell (20). This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures (38) may be formed in multiple-tiers to define a three-dimensional RRAM memory array (110). Further embodiments also provide a spacer pitch-doubled RRAM memory array (120) that integrates vertical memory cell structures (38).

Abstract translation: 本公开提供了用于形成可以在RRAM设备中实现的垂直存储器单元结构（38）的实施例。 在一个实施例中，可以通过改变字线（22）高度（ΔWL）和/或字线（22）界面（50）特性来增加存储器单元面积，以确保产生适于形成 导电路径通过RRAM存储器单元（20）的有源层（44）。 这可以保持连续体行为，同时减少在纳米尺度上经常遇到的随机细胞间变异性。 在另一个实施例中，这种垂直存储器单元结构（38）可以以多层形成以限定三维RRAM存储器阵列（110）。 另外的实施例还提供了集成垂直存储器单元结构（38）的间隔螺距加倍的RRAM存储器阵列（120）。

公开(公告)号：WO2013022560A3

公开(公告)日：2013-04-11

申请号：PCT/US2012046913

申请日：2012-07-16

Applicant: MICRON TECHNOLOGY INC ,  SILLS SCOTT E

Inventor： SILLS SCOTT E

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/1253 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1266 ,  H01L45/143 ,  H01L45/146

Abstract: Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.

Abstract translation: 一些实施例包括存储器单元。 存储单元可以包含一对电极之间的开关区域和离子源区域。 开关区域可以被配置为可逆地保持导电桥，当导电桥保持在开关区域内时，存储单元处于低电阻状态，并且当导电桥不在开关区域内时处于高电阻状态 。 存储器单元可以包含跨越开关区域延伸的有序框架，以将导电桥定向在开关区域内，其中框架在存​​储单元的高电阻和低电阻状态下保持在开关区域内。

公开(公告)号：WO2012141898A3

公开(公告)日：2013-01-31

申请号：PCT/US2012031004

申请日：2012-03-28

Applicant: MICRON TECHNOLOGY INC ,  SILLS SCOTT E ,  SANDHU GURTEJ

Inventor： SILLS SCOTT E ,  SANDHU GURTEJ

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1226 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: This disclosure provides embodiments for the formation of vertical memory cell structures (38) that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line (22) height (?WL) and/or word line (22) interface surface (50) characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer (44) of an RRAM memory cell (20). This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures (38) may be formed in multiple-tiers to define a three-dimensional RRAM memory array (110). Further embodiments also provide a spacer pitch-doubled RRAM memory array (120) that integrates vertical memory cell structures (38).

Abstract translation: 本公开提供了用于形成可以在RRAM设备中实现的垂直存储器单元结构（38）的实施例。 在一个实施例中，可以通过改变字线（22）高度（ΔWL）和/或字线（22）界面（50）特性来增加存储器单元面积，以确保产生适于形成 导电路径通过RRAM存储器单元（20）的有源层（44）。 这可以保持连续体行为，同时减少在纳米尺度上经常遇到的随机细胞间变异性。 在另一个实施例中，这种垂直存储器单元结构（38）可以以多层形成以限定三维RRAM存储器阵列（110）。 另外的实施例还提供了集成垂直存储器单元结构（38）的间隔螺距加倍的RRAM存储器阵列（120）。

公开(公告)号：WO2012125610A3

公开(公告)日：2012-12-06

申请号：PCT/US2012028878

申请日：2012-03-13

Applicant: MICRON TECHNOLOGY INC ,  TANG SANH D ,  SILLS SCOTT E ,  WEST WHITNEY L ,  GOODWIN ROB B ,  SINHA NISHANT

Inventor： TANG SANH D ,  SILLS SCOTT E ,  WEST WHITNEY L ,  GOODWIN ROB B ,  SINHA NISHANT

IPC: H01L21/28 ,  H01L21/8239

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：WO2012060993A3

公开(公告)日：2012-05-10

申请号：PCT/US2011/056281

申请日：2011-10-14

Applicant: MICRON TECHNOLOGY, INC. ,  SILLS, Scott, E. ,  MEADE, Roy, E.

Inventor： SILLS, Scott, E. ,  MEADE, Roy, E.

IPC: H01L21/8247 ,  H01L27/115 ,  H01L21/8242 ,  H01L27/108

Abstract: Some embodiments include methods of forming electrical components. First and second exposed surface configurations are formed over a first structure, and material is then formed across the surface configurations. The material is sub-divided amongst two or more domains, with a first of the domains being induced by the first surface configuration, and with a second of the domains being induced by the second surface configuration. A second structure is then formed over the material. The first domains of the material are incorporated into electrical components. The second domains may be replaced with dielectric material to provide isolation between adjacent electrical components, or may be utilized as intervening regions between adjacent electrical components.

公开(公告)号：WO2012125610A2

公开(公告)日：2012-09-20

申请号：PCT/US2012/028878

申请日：2012-03-13

Applicant: MICRON TECHNOLOGY, INC. ,  TANG, Sanh D. ,  SILLS, Scott E. ,  WEST, Whitney L. ,  GOODWIN, Rob B. ,  SINHA, Nishant

Inventor： TANG, Sanh D. ,  SILLS, Scott E. ,  WEST, Whitney L. ,  GOODWIN, Rob B. ,  SINHA, Nishant

IPC: H01L21/28 ,  H01L21/8239

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 为半导体结构和存储单元形成诸如互连和电极之类的导电元件的方法。 该方法包括在至少一个开口的一部分中形成包含银的第一导电材料和第二导电材料，并执行抛光工艺以用第一导电材料和第二导电材料中的至少一个填充该至少一个开口。 可以执行退火工艺以形成银和材料的混合物或合金。 该方法能够形成尺寸减小（例如，小于约20nm）的含银导电元件。 所得的导电元件具有理想的电阻率。 例如，该方法可用于形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了包括这种导电结构的半导体结构和存储单元。

公开(公告)号：WO2012060993A2

公开(公告)日：2012-05-10

申请号：PCT/US2011056281

申请日：2011-10-14

Applicant: MICRON TECHNOLOGY INC ,  SILLS SCOTT E ,  MEADE ROY E

Inventor： SILLS SCOTT E ,  MEADE ROY E

IPC: H01L21/8247 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L45/1666 ,  H01L21/76834 ,  H01L21/76883 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

Abstract: Some embodiments include methods of forming electrical components. First and second exposed surface configurations are formed over a first structure, and material is then formed across the surface configurations. The material is sub-divided amongst two or more domains, with a first of the domains being induced by the first surface configuration, and with a second of the domains being induced by the second surface configuration. A second structure is then formed over the material. The first domains of the material are incorporated into electrical components. The second domains may be replaced with dielectric material to provide isolation between adjacent electrical components, or may be utilized as intervening regions between adjacent electrical components.

Abstract translation: 一些实施例包括形成电气部件的方法。 在第一结构上形成第一和第二暴露表面结构，然后在表面结构上形成材料。 材料在两个或更多个区域中被细分，其中第一个区域由第一表面构造诱导，并且第二个区域由第二表面构造诱导。 然后在材料上形成第二结构。 材料的第一个领域被纳入电子元件。 第二区域可以被电介质材料替代以提供相邻电组件之间的隔离，或者可以被用作相邻电组件之间的中间区域。