公开(公告)号：WO2014127850A1

公开(公告)日：2014-08-28

申请号：PCT/EP2013/053883

申请日：2013-02-27

Applicant: ASELTA NANOGRAPHICS

Inventor： TIPHINE, Charles ,  QUAGLIO, Thomas ,  MARTIN, Luc

IPC: H01J37/302 ,  H01J37/317

CPC classification number: G06F17/5081 ,  B82Y10/00 ,  B82Y40/00 ,  G06F17/50 ,  H01J37/3026 ,  H01J37/3174 ,  H01J2237/31764 ,  H01J2237/31776

Abstract: The invention discloses a computer implemented method of fracturing a surface into elementary features (720a) wherein the desired pattern has a rectilinear or curvilinear form. Depending upon the desired pattern, a first fracturing will be performed of a non-overlapping or an overlapping type. If the desired pattern is resolution critical, it will be advantageous to perform a second fracturing step using eRIFs (730a). These eRIFs will be positioned either on the edges or on the medial axis (710a) or skeleton of the desired pattern. The invention further discloses method steps to define the position and shape of the elementary features used for the first and second fracturing steps.

Abstract translation: 本发明公开了一种将表面压裂成基本特征（720a）的计算机实现方法，其中期望的图案具有直线或曲线形式。 根据期望的图案，将执行非重叠或重叠类型的第一压裂。 如果期望的模式是分辨率关键的，则使用eRIF（730a）执行第二压裂步骤将是有利的。 这些eRIF将被定位在所需图案的边缘或中间轴（710a）或骨架上。 本发明还公开了用于限定用于第一和第二压裂步骤的基本特征的位置和形状的方法步骤。

公开(公告)号：WO2016102607A1

公开(公告)日：2016-06-30

申请号：PCT/EP2015/081059

申请日：2015-12-22

Applicant: ASELTA NANOGRAPHICS

Inventor： QUAGLIO, Thomas ,  MILLEQUANT, Mathieu ,  TIPHINE, Charles

IPC: G03F1/20 ,  G03F1/36 ,  G03F7/20

CPC classification number: G03F1/20 ,  G03F1/36 ,  G03F1/78 ,  G03F7/705 ,  G03F7/70508 ,  G03F7/70616

Abstract: The invention discloses an improved method of geometry corrections to be applied to properly transfer semiconductor designs on a wafer or a mask in nanometer scale processes. In contrast with some prior art techniques, geometry corrections and possibly dose corrections are applied before fracturing. Unlike edge based corrections, where the edges are displaced in parallel, the displacements applied to generated geometry corrections according to the invention do not preserve parallelism of the edges, which is specifically well suited for free form designs. A seed design is generated from the target design. Vertices connecting segments are placed along the seed design contour. Correction sites are placed on the segments. Displacement vectors are applied to the vertices. A simulated contour is generated and compared to the contour of the target design. The process is iterated until a match criteria between simulated and target design (or another stop criteria) is reached.

Abstract translation: 本发明公开了一种改进的几何校正方法，其应用于在纳米级工艺中在晶片或掩模上适当地转移半导体设计。 与一些现有技术相反，在压裂之前应用几何校正和可能的剂量校正。 不同于基于边缘的校正，其中边缘平行移位，应用于根据本发明的生成的几何校正的位移不保留边缘的平行度，其特别适合于自由形式设计。 从目标设计生成种子设计。 连接片段的顶点沿种子设计轮廓放置。 校正站点放置在段上。 位移向量应用于顶点。 生成模拟轮廓并与目标设计的轮廓进行比较。 迭代该过程，直到达到模拟和目标设计（或另一个停止标准）之间的匹配标准。