公开(公告)号：WO2005001840A2

公开(公告)日：2005-01-06

申请号：PCT/US2004015651

申请日：2004-05-18

Applicant: ATMEL CORP

Inventor： LOHEK BOHUMIL

IPC: G11C20060101 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  G11C

CPC classification number: H01L21/28273 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7887

Abstract: An arrangement of non-volatile memory transistors (11, 13, 15; 21, 23, 25; 31, 33, 35; etc.) constructed in symmetric pairs (14, 30) within the space defined by intersecting pairs of word (WL; 22, 24) and bit (BL; 10, 20) lines of a memory array. The transistors have spaced apart sources (32) and drains (34) separated by a channel and having a floating gate (28; 40, 42) over the channel characteristic of electrically erasable programmable read only memory transistors, except that there is no second poly gate. Only a single poly gate is used as a floating charge storage gate, which is placed sufficiently close to the source or drain of the device as to enable band-to-band tunneling. The single layer of poly has a T-shape, with a T-base (42) used as a floating gate and a T-top (40) extending over a word line in capacitive relation therewith. The word line is used to program and erase the floating gate in combination with a source or drain electrode. A block erase mode is available so that the arrangement of transistors can operate as a flash memory.

Abstract translation: 在由相交字对（WL，WL）定义的空间内以对称对（14,30）构造的非易失性存储器晶体管（11,13,15; 21,23,25; 31,33,35等） ; 22,24）和存储器阵列的位（BL; 10,20）行。 晶体管具有由沟道隔开的间隔开的源极（32）和漏极（34），并且在电可擦除可编程只读存储器晶体管的沟道特性上具有浮置栅极（28; 40,42），除了不存在第二聚 门。 只有一个多晶栅极用作浮动电荷存储栅极，其被放置得足够靠近器件的源极或漏极以实现带间隧穿。 单层多晶硅具有T形形状，具有用作浮置栅极的T型底座（42）和在与之电容性关系的字线上延伸的T型顶部（40）。 字线用于编程和擦除与源极或漏极结合的浮动栅极。 块擦除模式是可用的，因此晶体管的布置可以作为闪存进行操作。