公开(公告)号：WO2008008581A2

公开(公告)日：2008-01-17

申请号：PCT/US2007070612

申请日：2007-06-07

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L29/76 ,  H01L23/02

CPC classification number: H01L23/5227 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49541 ,  H01L24/05 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for producing passive components on an integrated circuit device (100). The integrated circuit device (100) has post wafer fabrication integrated passive components (107) situated on the opposite substrate side (105) of the device's integrated circuitry (103). Electrical contact pads (109) of the passive components (107) are configured to be coupled to the electronics package contact pads to complete the electronic package.

Abstract translation: 一种用于在集成电路器件（100）上产生无源部件的设备和方法。 集成电路器件（100）具有位于器件集成电路（103）的相对衬底侧（105）上的后置晶片制造集成无源部件（107）。 无源部件（107）的电接触垫（109）被配置为耦合到电子封装接触垫以完成电子封装。

公开(公告)号：WO2008008587A2

公开(公告)日：2008-01-17

申请号：PCT/US2007071079

申请日：2007-06-13

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/02

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for producing three- dimensional integrated circuit packages. In one embodiment, an electronics package (200) with at least two dice (207, 209) are stacked one atop another is disclosed. A top die (209) is of smaller size compared with a bottom die (207) such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die (207) contains contact pads (211) on the front side that couple with one or more passive components (213) fabricated on the back side of the top die (209) to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract translation: 一种用于生产三维集成电路封装的装置和方法。 在一个实施例中，公开了具有至少两个骰子（207,209）的电子封装（200）。 与底模（207）相比，顶模（209）尺寸较小，使得在芯片附接操作之后，底模的引线接合焊盘将被暴露以用于随后的引线接合操作。 底模（207）包括在前侧上的与在顶模（209）的背面上制造的一个或多个无源元件（213）耦合以便完成电路的接触焊盘（211）。 在另一个示例性实施例中，公开了一种在堆叠管芯封装中形成一个或多个三维无源部件的方法，其中部分电感器元件制造在底模的前侧和顶模的背面。 顶部和底部元件联接在一起，完成无源部件。

公开(公告)号：WO2008008586A3

公开(公告)日：2008-05-02

申请号：PCT/US2007070994

申请日：2007-06-12

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29355 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An apparatus and a method for packaging semiconductor devices (205, 207). Disclosed are multi- die packaging apparatuses (200) and techniques, especially useful for integrated circuit dice (207) involving insulative substrates (225), such as silicon- on-insulator (SOI), where grounding of a base layer (225) is not reasonably practical. Disclosed is a means for effectively grounding all layers of an integrated circuit device (205, 207) regardless of whether the device (205, 207) makes direct contact with a die-attach paddle (201).

Abstract translation: 一种封装半导体器件的装置和方法（205,207）。 公开了多芯片封装装置（200）和技术，尤其可用于涉及绝缘衬底（225）的绝缘衬底（225）（例如绝缘体上硅（SOI））的集成电路裸片（207），其中基底层 不合理实际。 公开了一种用于有效地将集成电路器件（205,207）的所有层接地的装置，而不管器件（205,207）是否与管芯附接板（201）直接接触。

公开(公告)号：WO2007127739A2

公开(公告)日：2007-11-08

申请号：PCT/US2007067315

申请日：2007-04-24

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49146 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus and a method for packaging semi-conductor devices. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels (213) formed through an encapsulation area (215) surrounding the device (207) and associated bond wires (211) are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads (205) to an uppermost portion of the encapsulated area (215) . The sacrificial metal base strip (201) serves as a plating bus and is etch-removed after plating. The filled tunnels (213) allow components to be stacked in a three-dimensional configuration.

Abstract translation: 一种用于封装半导体器件的装置和方法。 该设备适用于许多类型的使用牺牲金属基底条的当代包装方案。 通过围绕设备（207）和相关联的接合线（211）的封装区域（215）形成的隧道（213）通过例如电镀被金属导体填充，并将底部接触焊盘（205）延伸到最上部 的封装区域（215）。 牺牲金属基带（201）用作电镀母线，并且在电镀之后被蚀刻去除。 填充的隧道（213）允许组件以三维配置堆叠。

公开(公告)号：WO2008027694A3

公开(公告)日：2008-08-21

申请号：PCT/US2007075191

申请日：2007-08-03

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L24/45 ,  H01L24/73 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus includes a substrate strip component (201A-201E) of a leadless three-dimensional stackable semiconductor package (300) having mounting contacts on, for example, four peripheral edges. The substrate strip may either be fabricated for mounting a single electrical component (e.g., an integrated circuit die 209) or a plurality of substrate strips may be laid out in an X-Y matrix pattern which may later be singulated (215) into individual package strip for leadless packages. Three-dimensional stacking (350) is achieved by a bonding area (301) on an uppermost portion of the sidewall (203). The sidewall of the strip is high enough to enclose an encapsulant (213) covering a later mounted integrated circuit die and associated bonding wires (211).

Abstract translation: 一种用于封装半导体器件的装置和方法。 该装置包括在例如四个外围边缘上具有安装触点的无引线三维可堆叠半导体封装（300）的衬底条部件（201A-201E）。 衬底条可以被制造用于安装单个电气部件（例如，集成电路裸片209），或者可以以XY矩阵图案布置多个衬底条，其可以随后被单独化（215）到单独的封装条中，用于 无引线封装 通过侧壁（203）的最上部的接合区域（301）实现三维堆叠（350）。 条的侧壁足够高以封闭覆盖稍后安装的集成电路管芯和相关联的接合线（211）的密封剂（213）。

公开(公告)号：WO2008057896A3

公开(公告)日：2008-07-31

申请号：PCT/US2007083251

申请日：2007-10-31

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L21/00

CPC classification number: H05K1/185 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24011 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19042 ,  H05K3/4602 ,  H05K2203/0165 ,  H05K2203/085 ,  H05K2203/1469 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic multi -component package (74, 75) is assembled by placing multiple electronic components (30) within multiple openings (16) of a package substrate (12), then depositing and curing adhesive filler (34) in gaps between the components and the inner peripheries of the openings. Circuit features (38, 42), including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces (22F, 22B) of the package substrate. Preformed conductive vias (18) through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components (50, 54, 58) may be attached (52, 56, 60) to conductive lands on at least one side of the package. The circuit features also include contact pads (66) for external package connections, such as in a ball-grid-array or equivalent structure.

Abstract translation: 通过将多个电子部件（30）放置在封装基板（12）的多个开口（16）内，然后将粘合剂填料（34）沉积并固化在组件之间的间隙中并组装，并组装电子多组件封装（74,75） 开口的内周。 包括导电互连的电路特征（38,42）通过在封装衬底的前表面和后表面（22F，22B）上的薄膜光刻形成。 通过封装衬底的预成形导电通孔（18）提供了在相对衬底表面上的电路特征之间的电连接。 另外的电子部件（50,54,58）可以附接到封装的至少一侧上的导电焊盘（52,56,60）。 电路特征还包括用于外部封装连接的接触焊盘（66），例如以球栅阵列或等效结构。

公开(公告)号：WO2008057739A3

公开(公告)日：2008-07-10

申请号：PCT/US2007082002

申请日：2007-10-19

Applicant: ATMEL CORP ,  LAM KEN M

Inventor： LAM KEN M

IPC: H01L23/02

CPC classification number: H01L25/105 ,  H01L21/6835 ,  H01L24/97 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An apparatus and a method for packaging semiconductor devices. The apparatus is a three- dimensional electronic package comprising one or more electronic components (305, 307, 355, 357), a plurality of electrical contact pads (333, 335), and a plurality of electrically conductive three-dimensional plugs (315) formed through an encapsulant (311, 361). Specific ones of the plurality of electrical contact pads (333, 335) are electrically coupled to the one or more electronic components (305, 307, 355, 357) on an uppermost surface of the plurality of electrical contact pads (333, 335). The encapsulant (311, 361) is formed over and covers the one or more electronic devices (305, 307, 355, 357). The plurality of three-dimensional plugs (315) have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads (333, 335) and a second end extending substantially to an uppermost surface of the encapsulant (311, 361).

Abstract translation: 一种用于封装半导体器件的装置和方法。 该装置是包括一个或多个电子部件（305,307,355,357），多个电接触焊盘（333,335）和多个导电三维插头（315）的三维电子封装件， 通过密封剂（311,361）形成。 多个电接触焊盘（333,335）中的特定的电接触焊盘电耦合到多个电接触焊盘（333,335）的最上表面上的一个或多个电子部件（305,307,355,357）。 密封剂（311,361）形成在一个或多个电子设备（305,307,355,357）之上并且覆盖该一个或多个电子设备。 多个三维插头（315）具有从多个电接触焊盘（333,335）中的一个或多个的至少最上部延伸的第一端和基本上延伸到密封剂的最上表面的第二端 （311,361）。

公开(公告)号：WO2006044061A3

公开(公告)日：2009-04-09

申请号：PCT/US2005032386

申请日：2005-09-09

Applicant: ATMEL CORP

Inventor： LAM KEN M

IPC: H01L23/495

CPC classification number: H01L24/49 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48669 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48769 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48869 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85469 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/00012

Abstract: An electrical package for an integrated circuit die (101) which comprises a die-attach paddle (201) for mounting the integrated circuit die (101). The die­-attach paddle (201) has at least one down-set area located on a periphery of the die-attach paddle (201). The down-set area has an upper surface and a lower surface, with the upper surface configured to electrically couple a first end of a first electrically conductive lead wire (301). A second end of the first electrically conductive lead wire (301) is bonded to the integrated circuit die (101). The upper surface is further configured to electrically couple a first end of a second electrically conductive lead wire (303) and a second end of the second electrically conductive lead wire (303) is bonded to a lead finger (203) of the electrical package.

Abstract translation: 一种用于集成电路管芯（101）的电气封装件，包括用于安装集成电路管芯（101）的管芯附着焊盘（201）。 管芯附着桨（201）具有位于管芯附着桨（201）的周边上的至少一个下降区域。 下降区域具有上表面和下表面，其中上表面被配置为电耦合第一导电引线（301）的第一端。 第一导电引线（301）的第二端接合到集成电路管芯（101）。 上表面还被配置为电耦合第二导电引线（303）的第一端并且第二导电引线（303）的第二端被接合到电气封装的引线指（203）。

公开(公告)号：WO2005034178A2

公开(公告)日：2005-04-14

申请号：PCT/US2004028495

申请日：2004-09-02

Applicant: ATMEL CORP

Inventor： LAM KEN M ,  KOVATS JULIUS A

IPC: H01L21/673 ,  H01L21/687 ,  H01L

CPC classification number: H01L21/68778 ,  G01R1/0483 ,  H01L21/67346 ,  H01L21/68785

Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier (100) for temporarily mounting a non-wafer form device. The low-profile carrier (100) holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses (105, 107) which are machined or otherwise formed in the low-profile carrier (100).

Abstract translation: 本发明允许在标准自动晶片 - 探针测试器或半导体或相关行业（例如，平板显示器，数据存储等）过程中常用的其他自动化测试或测量设备上测试非晶片形式的器件。 本发明通过提供用于临时安装非晶片形式装置的低轮廓载体（100）来实现这一点。 低轮廓载体（100）将非晶片形成装置（例如集成电路芯片，薄膜头结构，一个或多个模制阵列封装等）磁性地保持在机加工的凹部（105,107）中 或以其他方式形成在薄型载体（100）中。

公开(公告)号：WO0182361A3

公开(公告)日：2002-05-16

申请号：PCT/US0111035

申请日：2001-04-04

Applicant: ATMEL CORP

Inventor： LAM KEN M

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/4985 ,  H01L24/02 ,  H01L24/06 ,  H01L24/11 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06102 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83856 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01043 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming an integrated circuit package at the wafer level. The integrated circuit package occupies a minimum amount of space on an end-use printed circuit board. Solder bumps (30), or conductive adhesive, is deposited on the metallized wirebond pads (23) on the top surface of a silicon wafer (21). An underfill-flux material (27) is deposited over the wafer (21) and the solder bumps (30). A pre-fabricated interposer substrate (31), made of a metal circuitry (34) and a dielectric base (32), has a plurality of metallized through-holes (38) which are aligned with the solder bumps (30). The wafer/interposer assembly is reflowed, or cured, to form the electrical connection between the circuitry on the interposer layer (34) and the circuitry on the wafer. Solder balls (50) are then placed on the metal pad openings on the interposer substrate and are reflowed to form a wafer-level BGA structure. The wafer-level BGA structure is then cut into individual BGA chip packages.

Abstract translation: 一种在晶片级形成集成电路封装的方法。 集成电路封装在最终用途的印刷电路板上占用最小的空间。 焊料凸块（30）或导电粘合剂沉积在硅晶片（21）的顶表面上的金属化引线焊盘（23）上。 在晶片（21）和焊料凸块（30）上沉积底部填充助焊剂材料（27）。 由金属电路（34）和电介质基底（32）制成的预制插入器基板（31）具有与焊料凸块（30）对准的多个金属化通孔（38）。 晶片/插入器组件被回流或固化，以形成插入层（34）上的电路与晶片上的电路之间的电连接。 然后将焊球（50）放置在插入器基板上的金属焊盘开口上并被回流以形成晶片级BGA结构。 然后将晶片级BGA结构切割成单独的BGA芯片封装。