公开(公告)号：WO2014070705A1

公开(公告)日：2014-05-08

申请号：PCT/US2013/067206

申请日：2013-10-29

Applicant: CREE, INC.

Inventor： HAGLEITNER, Helmut ,  RADULESCU, Fabian ,  NAMISHIA, Daniel

IPC: H01L21/285 ,  H01L29/47

CPC classification number: H01L21/28581 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7787

Abstract: Embodiments of a Nickel-rich (Ni-rich) Schottky contact for a semiconductor device and a method of fabrication thereof are disclosed. Preferably, the semiconductor device is a radio frequency or power device such as, for example, a High Electron Mobility Transistor (HEMT), a Schottky diode, a Metal Semiconductor Field Effect Transistor (MESFET), or the like. In one embodiment, the semiconductor device includes a semiconductor body and a Ni-rich Schottky contact on a surface of the semiconductor body. The Ni-rich Schottky contact includes a multilayer Ni-rich contact metal stack. The semiconductor body is preferably formed in a Group III nitride material system (e.g., includes one or more Gallium Nitride (GaN) and/or Aluminum Gallium Nitride (AlGaN) layers). Because the Schottky contact is Ni-rich, leakage through the Schottky contact is substantially reduced.

Abstract translation: 公开了用于半导体器件的富镍（富Ni）肖特基接触的实施例及其制造方法。 优选地，半导体器件是射频或功率器件，例如高电子迁移率晶体管（HEMT），肖特基二极管，金属半导体场效应晶体管（MESFET）等。 在一个实施例中，半导体器件在半导体本体的表面上包括半导体本体和富Ni肖特基接触。 富Ni肖特基接触包括多层富Ni接触金属叠层。 半导体本体优选地形成在III族氮化物材料系统中（例如，包括一个或多个氮化镓（GaN）和/或氮化铝镓（AlGaN）层）。 由于肖特基接触是富Ni，所以通过肖特基接触的泄漏显着降低。

公开(公告)号：WO2021247276A2

公开(公告)日：2021-12-09

申请号：PCT/US2021/033981

申请日：2021-05-25

Applicant: CREE, INC.

Inventor： ALCORN, Terry ,  NAMISHIA, Daniel ,  RADULESCU, Fabian

IPC: H03F3/195 ,  H01L23/66 ,  H01L25/16 ,  H01L29/66 ,  H01L21/70 ,  H01L23/495 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8258 ,  H01L2223/6655 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48157 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2224/94 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/49531 ,  H01L23/498 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/0694 ,  H01L2924/10156 ,  H01L2924/1421 ,  H01L2924/19107

Abstract: An integrated circuit device includes a radio frequency transistor amplifier die having a first surface, a second surface, a semiconductor layer structure that is between the first and second surfaces and includes a plurality of transistor cells adjacent the first surface, and terminals coupled to the transistor cells. At least one passive electronic component is provided on the second surface of the die and is electrically connected to at least one of the terminals, for example, by at least one conductive via. One or more conductive pillar structures may protrude from the first surface of the die to provide electrical connections to one or more of the terminals.

公开(公告)号：WO2014158308A1

公开(公告)日：2014-10-02

申请号：PCT/US2014/011286

申请日：2014-01-13

Applicant: CREE, INC.

Inventor： RING, Zoltan ,  HAGLEITNER, Helmut ,  NAMISHIA, Daniel

IPC: H01L23/31

CPC classification number: H01L21/56 ,  H01L23/3135 ,  H01L23/3192 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm 2 ). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.

Abstract translation: 公开了用于半导体器件的多层环境屏障的实施例及其制造方法。 在一个实施例中，半导体器件形成在半导体管芯上。 半导体管芯包括在半导体本体上的半导体本体和钝化结构。 在钝化结构上提供多层环境屏障。 多层环境屏障是将半导体器件与环境气密密封的低缺陷多层电介质膜。 在一个实施例中，多层环境屏障的缺陷密度小于每平方厘米10个缺陷（cm2）。 通过具有低缺陷密度，多层环境屏障用作对环境的坚固屏障。

公开(公告)号：WO2014137622A1

公开(公告)日：2014-09-12

申请号：PCT/US2014/017663

申请日：2014-02-21

Applicant: CREE, INC.

Inventor： HANEY, Sarah, Kay ,  HULL, Brett ,  NAMISHIA, Daniel

IPC: H01L23/485 ,  H01L29/417

CPC classification number: H01L23/48 ,  H01L21/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L29/41741 ,  H01L29/42308 ,  H01L29/42372 ,  H01L29/74 ,  H01L29/7802 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/056 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/0612 ,  H01L2224/06181 ,  H01L2224/29101 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/38 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device, comprising: a substrate (50) with an active area (44) and a gate control contact area (52); a source bond pad (46) on at least a portion of the active area (44); a gate bond pad (48) over the gate control contact area (52) and laterally extending over a portion of the source bond pad (46); and dielectric layer (60) between the portion of the source bond pad (46) and the gate control bond pad (48). The arrangement of the gate bond pad (48) partiall on top of the source bond pad (46) enables the active area (44) to extend below the gate bond pad (48), which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area (44) and thus a rated current for a particular semiconductor die size. Methods for manufacturing said semiconductor device are also provided.

Abstract translation: 一种半导体器件，包括：具有有源区（44）和栅控制接触区（52）的衬底（50）; 在所述有源区域（44）的至少一部分上的源极焊盘（46）; 位于所述栅极控制接触区域（52）的上方并在所述源极接合焊盘（46）的一部分上横向延伸的栅极接合焊盘（48）; 以及在所述源极焊盘（46）的所述部分与所述栅极控制接合焊盘（48）之间的介电层（60）。 栅极接合焊盘（48）在源极接合焊盘（46）的顶部上的布置使得有源区域（44）能够延伸到栅极接合焊盘（48）下方，栅极接合焊盘（48）进一步减小功率半导体器件 对于特定的额定电流，或相反地，增加有源区（44）的尺寸，并因此增加特定半导体晶粒尺寸的额定电流。 还提供了制造所述半导体器件的方法。

公开(公告)号：WO2019108339A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/058836

申请日：2018-11-02

Applicant: CREE, INC.

Inventor： HARDIMAN, Chris ,  LEE, Kyoung-Keun ,  RADULESCU, Fabian ,  NAMISHIA, Daniel ,  SHEPPARD, Scott, Thomas

IPC: H01L23/31 ,  H01L29/06

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.