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    CHANNEL SELECT FILTER APPARATUS AND METHOD
    1.
    发明申请
    CHANNEL SELECT FILTER APPARATUS AND METHOD 审中-公开

    公开(公告)号：WO2010088293A3

    公开(公告)日：2010-08-05

    申请号：PCT/US2010/022266

    申请日：2010-01-27

    Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

    Inventor： MALLINSON, Andrew, Martin

    IPC: H03H17/00

    Abstract: Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non- radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital- to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition.

    DIGITAL TO ANALOG CONVERTER HAVING A LOW POWER SEMI-ANALOG FINITE IMPULSE RESPONSE CIRCUIT
    2.
    发明申请
    DIGITAL TO ANALOG CONVERTER HAVING A LOW POWER SEMI-ANALOG FINITE IMPULSE RESPONSE CIRCUIT 审中-公开
    具有低功耗半模拟有限脉冲响应电路的数字转换器

    公开(公告)号：WO2004107583A1

    公开(公告)日：2004-12-09

    申请号：PCT/US2003/016567

    申请日：2003-05-22

    Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

    Inventor： MALLINSON, Andrew, Martin

    IPC: H03M1/66

    CPC classification number: H03M3/504

    Abstract: A circuit is provided having a secondary semi-analog FIR filter (100) connected to a primary filter via a coefficient to reduce the size of the sizes of the resistors (106) used in the primary filter. The coefficient may be one or more intermediate resistors connected between separate resistor/voltage driver banks that make up the FIR filter (100). The result is a circuit that takes up less chip space required to accommodate the required resistance for a digital to analog converter (DAC). The invention configures the resistor structure to produce the same output result as a conventional circuit, but with a smaller resistor values that take up less surface area on the chip.

    Abstract translation: 提供了具有通过系数连接到初级滤波器的次级半模拟FIR滤波器（100）以减小在主滤波器中使用的电阻器（106）尺寸的尺寸的电路。 该系数可以是连接在构成FIR滤波器（100）的分离电阻器/电压驱动器组之间的一个或多个中间电阻器。 结果是一个电路占用更少的芯片空间，以适应数模转换器（DAC）所需的电阻。 本发明构造了电阻器结构以产生与常规电路相同的输出结果，但是具有较小的电阻值，其在芯片上占据较小的表面积。

    HIGH SPEED HIGH GAIN AMPLIFIER
    4.
    发明申请
    HIGH SPEED HIGH GAIN AMPLIFIER 审中-公开
    高速高增益放大器

    公开(公告)号：WO2004098044A1

    公开(公告)日：2004-11-11

    申请号：PCT/US2003/009633

    申请日：2003-03-27

    Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

    Inventor： MALLINSON, Andrew, Martin

    IPC: H03F1/00

    CPC classification number: H03F3/343 ,  H03F2200/453

    Abstract: An electronic device (300) is provided such as an amplifier, for example, having improved gain and transconductance and low output impedance. The device includes a primary amplifier "M1" configured to carry an operating load. The device includes an input "In" for receiving an input signal, and an output "Out" for outputting an output signal, and operates having a variable output, as it carries an operational load. The device (300) further includes a secondary amplifier "M2" configured to operate at a fixed operating condition, not burdened by carrying an operational load, and includes a secondary input "In" configured to receive the input signal, wherein the secondary amplifier is configured to define the input voltage. The device (300) is configured to detect a difference in operating current between the primary and secondary amplifiers, and to compensate for any operational load that may be applied to the primary amplifier during operation.

    Abstract translation: 提供了诸如具有改善的增益和跨导和低输出阻抗的放大器的电子设备（300）。 该装置包括被配置为承载操作负载的初级放大器“M1”。 该装置包括用于接收输入信号的输入“In”和用于输出输出信号的输出“Out”，并且在其承载操作负载时操作具有可变输出。 装置（300）还包括辅助放大器“M2”，其被配置为在固定工作状态下工作，而不承担运行负载，并且包括被配置为接收输入信号的次级输入“In”，其中次级放大器 配置为定义输入电压。 器件（300）被配置为检测初级和次级放大器之间的工作电流的差异，并且补偿在操作期间可能施加到初级放大器的任何操作负载。

    IMPROVED VOLTAGE SEGMENTED DIGITAL TO ANALOG CONVERTER
    5.
    发明申请
    IMPROVED VOLTAGE SEGMENTED DIGITAL TO ANALOG CONVERTER 审中-公开
    改进的电压SEGMENTED数字到模拟转换器

    公开(公告)号：WO2004088848A2

    公开(公告)日：2004-10-14

    申请号：PCT/US2004/009349

    申请日：2004-03-26

    Applicant: ESS TECHNOLOGY INC. ,  MALLINSON, Andrew, Martin

    Inventor： MALLINSON, Andrew, Martin

    IPC: H03M

    CPC classification number: H03M1/0604 ,  H03M1/682 ,  H03M1/765

    Abstract: An improved segmented analog to digital converter is provided, configured with a novel method of compensating current flow in secondary or successive segmented elements. In operation, dual current devices initially load, then subsequently unload a cascade of resistor networks connected to the secondary or successive voltage segmenting elements, preventing the perturbation of precise operation of the primary or preceding elements. In contrast to conventional approaches, the improved converter obviates the need for a buffer or amplifier to isolate the secondary and successive voltage segmenting elements from the primary or preceding elements.

    Abstract translation: 提供了一种改进的分段模数转换器，其配置有补偿次级或连续分段元件中的电流的新颖方法。 在操作中，双电流装置最初加载，随后卸载连接到次级或连续电压分段元件的级联的电阻网络，以防止主要或先前元件的精确操作的扰动。 与常规方法相比，改进的转换器不需要缓冲器或放大器来隔离次级和连续的电压分段元件与初级元件或先前元件。

    FREQUENCY SHAPING STREAM SIGNAL PROCESSOR
    6.
    发明申请
    FREQUENCY SHAPING STREAM SIGNAL PROCESSOR 审中-公开

    公开(公告)号：WO2004088642A3

    公开(公告)日：2004-10-14

    申请号：PCT/US2004/009351

    申请日：2004-03-26

    Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

    Inventor： MALLINSON, Andrew, Martin

    IPC: H03C3/00

    Abstract: A signal processor (100) has a plurality of channels, each channel configured to receive an input signal stream (S1~S8), to reduce the signal to a direct current signal and to process the signal according to the stream signal. Each channel also has a plurality of low pass filters (LPF~LPF_4) configured to filter in-phase and quadrature-phase modulator outputs with a first low pass filter and to filter a reference quadrature signals, and a gain control (Gain J) configured to re-modulate gain adjusted output signals with the filtered quadrature signals. The processor further includes an inverter (214) to invert the in-phase filtered reference signal and means to multiply (216) the quadrature gain adjusted output signal.

    ANALOG-TO-DIGITAL CONVERTER
    7.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER 审中-公开
    模拟数字转换器

    公开(公告)号：WO2004068719A1

    公开(公告)日：2004-08-12

    申请号：PCT/US2003/009041

    申请日：2003-03-26

    Applicant: ESS TECHNOLOGY, INC. ,  MALLINSON, Andrew, Martin

    Inventor： MALLINSON, Andrew, Martin

    IPC: H03M1/36

    CPC classification number: H03M1/0854 ,  H03M1/1235 ,  H03M1/144 ,  H03M1/206 ,  H03M1/367

    Abstract: An analog-to-digital converter (300) in which each of a plurality of comparators is, in a successive approximation manner, selectively enabled or disabled and the outputs from those comparators summed together to produce a digital signal therefrom.

    Abstract translation: 一种模数转换器（300），其中多个比较器中的每一个以逐次逼近的方式被选择性地使能或禁止，并且来自那些比较器的输出相加在一起从而产生数字信号。

    DIFFERENTIAL INPUT FLASH ANALOG TO DIGITAL CONVERTER
    8.
    发明申请
    DIFFERENTIAL INPUT FLASH ANALOG TO DIGITAL CONVERTER 审中-公开
    差分输入闪存模拟数字转换器

    公开(公告)号：WO2003088498A1

    公开(公告)日：2003-10-23

    申请号：PCT/US2003/005813

    申请日：2003-02-25

    Applicant: ESS TECHNOLOGY, INC.

    Inventor： MALLINSON, Andrew, Martin

    IPC: H03M1/36

    CPC classification number: H03M1/367

    Abstract: A differential input flash analog to digital converter (500) in which an array of comparators "C1,1-C1,5" is connected to compare reference signals within a parabolic distribution of such signals generated by the application of a differential input signals "Vin(a)-Vin(b)" across an impedance network "R1-R5". The comparator array comprises at least two pluralities of comparators, the first plurality of comparators comparing pairs of reference nodes separated by a first step size, the second plurality of comparators comparing pairs of reference nodes separated by a second step size. Preferably, the comparator array further comprises a third plurality of comparators comparing pairs of reference nodes separated by a third step size, but only where necessary to maximize the available comparison range.

    Abstract translation: 差分输入闪存模数转换器（500），其中比较器“C1,1-C1,5”的阵列被连接以比较通过应用差分输入信号“Vin”生成的这种信号的抛物面分布内的参考信号 （a）-Vin（b）“跨阻抗网络”R1-R5“。 所述比较器阵列包括至少两个比较器，所述第一多个比较器比较由第一步长分隔的参考节点对，所述第二多个比较器比较由第二步长分隔的参考节点对。 优选地，比较器阵列还包括第三多个比较器，其将由第三步长分隔的参考节点对进行比较，但仅在必要时才使可用比较范围最大化。

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