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公开(公告)号：WO2016048318A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057364
申请日：2014-09-25
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： BUCHANAN, Brent , SHARMA, Amit S , GIBSON, Gary , ORDENTLICH, Erik , MURALIMANOHAR, Naveen
IPC: G11C8/10
CPC classification number: G11C8/10 , G11C13/0023 , G11C13/0026 , G11C13/0028
Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.
Abstract translation: 本文公开的示例实现可以用于解码交叉点阵列中的存储器元件。 在一个示例实现中，漏极电压被施加到与所选存储器元件相关联的交叉点阵列中的所选行的场效应晶体管开关的漏极端子。 用于所选行的场效应晶体管开关的体积端子可以利用独立于漏极，源极或衬底电压的阱电压来偏置。 在这种示例中，用于所选行的场效应晶体管开关的栅极端子可以由包括漏极电压和阱电压的栅极电压驱动。 选择漏极电压，阱电压和栅极电压，使所选行的场效应晶体管开关作为欧姆开关工作。
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公开(公告)号：WO2016068992A1
公开(公告)日：2016-05-06
申请号：PCT/US2014/063394
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： MURALIMANOHAR, Naveen , ORDENTLICH, Erik , JEON, Yoocharn
CPC classification number: G11C13/004 , G11C13/0007 , G11C13/0023 , G11C13/003 , G11C13/0069 , G11C27/02 , G11C2013/0054 , G11C2013/0057 , G11C2013/0066 , G11C2213/77
Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.
Abstract translation: 访问两个存储器单元的方法包括：从第一位线的第一存取电流中减去与第一存储单元相关联的潜行电流来确定流过第一存储器单元的第一单元电流，并且确定流过第二存储器的第二单元电流 通过从第一位线或第二位线的第二访问电流中减去与第一存储器单元相关联的潜行电流，在第一位线中的单元或第二位线。
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公开(公告)号：WO2016068980A1
公开(公告)日：2016-05-06
申请号：PCT/US2014/063330
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： FOLTIN, Mark , YOOCHARN, Jeon , BUCHANAN, Brent , ORDENTLICH, Erik , MURALIMANOHAR, Naveen , IGNOWSKI, James S. , INGEMI, Jacquelyn M.
CPC classification number: G11C13/004 , G11C7/06 , G11C13/0038 , G11C13/0059 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2207/068
Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.
Abstract translation: 本公开提供了一种电路，其包括斜坡发生器以向电阻存储器单元施加电压斜坡。 感测电路可以响应于所施加的电压斜坡使得斜坡发生器能够监视从电阻存储器单元接收的电流输出，其中感测电路将电流输出与预定电流阈值进行比较，以确定电阻性存储单元的状态。
