公开(公告)号：WO2022066354A1

公开(公告)日：2022-03-31

申请号：PCT/US2021/047748

申请日：2021-08-26

Applicant: INTEL CORPORATION

Inventor： THEN, Han Wui ,  RADOSAVLJEVIC, Marko ,  KOIRALA, Pratik ,  THOMAS, Nicole K. ,  FISCHER, Paul B. ,  ELSHERBINI, Adel A. ,  TALUKDAR, Tushar ,  SWAN, Johanna M. ,  GOMES, Wilfred ,  CHAU, Robert S. ,  CHOI, Beomseok

IPC: H01L27/06 ,  H01L29/20 ,  H01L27/092 ,  H01L21/8238

Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

公开(公告)号：WO2019066870A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054111

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： BHARATH, Krishna ,  RADHAKRISHNAN, Kaladhar ,  LAMBERT, William ,  HILL, Michael ,  CHOI, Beomseok

IPC: H01L23/60 ,  H01L23/52 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a substrate; a die coupled to the substrate; at least two active devices positioned in the substrate; a plurality of vias surrounding at least one of the two active devices such that a Faraday cage is formed around the at least one of the two active devices.

公开(公告)号：WO2019066865A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054071

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： LAMBERT, William J. ,  RADHAKRISHNAN, Kaladhar ,  CHOI, Beomseok ,  BHARATH, Krishna ,  HILL, Michael J.

IPC: G05F3/02

CPC classification number: H02M3/1584 ,  H02M3/158 ,  H02M2001/0032 ,  H02M2001/0048 ,  H02M2001/008 ,  H02M2003/1566

Abstract: An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.