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公开(公告)号：WO2019117975A1
公开(公告)日：2019-06-20
申请号：PCT/US2017/066891
申请日：2017-12-17
Applicant: INTEL CORPORATION
Inventor： LAMPERT, Lester , ROBERTS, Jeanette M. , CAUDILLO, Roman , YOSCOVITS, Zachary R. , MICHALAK, David J. , CLARKE, James S. , GEORGE, Hubert C. , PILLARISETTY, Ravi , THOMAS, Nicole K. , SINGH, Kanwaljit
IPC: H01L29/15 , H01L29/66 , H01L29/80 , H01L25/065
Abstract: Embodiments of the present disclosure propose an approach to integrating TSVs into substrates on which quantum circuits are built. The approach is based on providing an etch-stop layer over the qubit side of a substrate, in order to protect the qubit side, and performing the necessary processing to form the TSVs from the backside of the substrate. Namely, an etch is performed on the backside of the substrate to form via openings extending through the substrate and stopping at the etch-stop layer, and, following the etch, a superconductive material is conformally deposited into the openings, thus lining the sidewalls of the openings and supported at the bottom of the openings by the etch-stop layer. The remaining volume of the openings may then be filled with a fill material. After that, the etch-stop layer may be removed and qubits devices may be provided on the qubit side of the substrate.
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公开(公告)号：WO2019117883A1
公开(公告)日：2019-06-20
申请号：PCT/US2017/065932
申请日：2017-12-13
Applicant: INTEL CORPORATION
Inventor： YOSCOVITS, Zachary R. , LAMPERT, Lester , CAUDILLO, Roman , ROBERTS, Jeanette M. , GEORGE, Hubert C. , THOMAS, Nicole K. , SINGH, Kanwaljit , MICHALAK, David J. , PILLARISETTY, Ravi , CLARKE, James S.
Abstract: One aspect of the present disclosure proposes a method of fabricating quantum circuit assemblies that include Josephson Junctions. The method is based on providing a structure that forms a bridge or a cantilever over a lead for the bottom electrode of a future Josephson Junction, forming an opening in the bridge/cantilever so that the opening is above the lead for the bottom electrode, and then depositing bottom and top electrode materials, as well as the tunnel barrier material for the Josephson Junction, through the opening. Such a method may result in Josephson Junctions having an improved performance compared to Josephson Junctions fabricated using existing techniques, and may be efficiently used in large-scale manufacturing.
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公开(公告)号：WO2018164656A1
公开(公告)日：2018-09-13
申请号：PCT/US2017/020855
申请日：2017-03-06
Applicant: INTEL CORPORATION
Inventor： THOMAS, Nicole K. , PILLARISETTY, Ravi , GEORGE, Hubert C. , RACHMADY, Willy , LE, Van H. , CLARKE, James S. , AMIN, Payam , SINGH, Kanwaljit , ROBERTS, Jeanette M. , CAUDILLO, Roman , YOSCOVITS, Zachary R. , MICHALAK, David J.
IPC: H01L29/06 , H01L29/423 , H01L29/775 , H01L29/66
Abstract: Disclosed herein are quantum nanowire devices, and related methods and computing devices. In some embodiments, a quantum nanowire device may include: a plurality of nanowires parallel to each other; a first gate surrounding individual ones of the one or more nanowires; and a second gate surrounding individual ones of the one or more nanowires, wherein the first gate and the second gate are spaced apart.
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公开(公告)号：WO2018160184A1
公开(公告)日：2018-09-07
申请号：PCT/US2017/020561
申请日：2017-03-03
Applicant: INTEL CORPORATION
Inventor： ROBERTS, Jeanette M. , PELLERANO, Stefano , CLARKE, James S. , ELSHERBINI, Adel A. , CAUDILLO, Roman , YOSCOVITS, Zachary R. , MICHALAK, David J. , PILLARISETTY, Ravi , GEORGE, Hubert C. , THOMAS, Nicole K. , SINGH, Kanwaljit
CPC classification number: H01P3/006
Abstract: Described herein are new transmission line structures for use as resonators and non-resonant transmission lines in quantum circuits. In one aspect of the present disclosure, a proposed structure includes a lower ground plane structure disposed over or in the substrate, a dielectric layer disposed over the lower ground plane structure, a first and a second upper ground plane structures disposed over the dielectric layer and electrically connected to the lower ground plane structure, and a signal line structure disposed over the dielectric layer, between the first and the second upper ground plane structures. Transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to control the qubits. Methods for fabricating such structures are disclosed as well.
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公开(公告)号：WO2018143986A1
公开(公告)日：2018-08-09
申请号：PCT/US2017/016130
申请日：2017-02-02
Applicant: INTEL CORPORATION
Inventor： GEORGE, Hubert C. , CLARKE, James S. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , THOMAS, Nicole K. , YOSCOVITS, Zachary R. , CAUDILLO, Roman , AMIN, Payam
IPC: H01L49/00 , H01L29/775 , H01L29/66
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a plurality of pillars, wherein individual pillars include a quantum well layer, at least two of the pillars are spaced apart in a first dimension, at least two of the pillars are spaced apart in a second dimension, and the first and second dimensions are perpendicular; an insulating material between at least two of the pillars spaced apart in the first dimension and at least two of the pillars spaced apart in the second dimension; and a plurality of gates disposed above corresponding individual ones of the pillars.
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公开(公告)号：WO2018125026A1
公开(公告)日：2018-07-05
申请号：PCT/US2016/068629
申请日：2016-12-27
Applicant: INTEL CORPORATION
Inventor： ROBERTS, Jeanette M. , ELSHERBINI, Adel A. , LIFF, Shawna , SWAN, Johanna M. , CAUDILLO, Roman , YOSCOVITS, Zachary R. , THOMAS, Nicole K. , PILLARISETTY, Ravi , GEORGE, Hubert C. , CLARKE, James S.
Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.
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公开(公告)号：WO2018063287A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054668
申请日：2016-09-30
Applicant: INTEL CORPORATION
Inventor： MAJHI, Prashant , KARPOV, Elijah V. , MUKHERJEE, Niloy , CLARKE, James S. , PILLARISETTY, Ravi
CPC classification number: G11C13/0011 , G11C13/00 , G11C2013/0083 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/124 , H01L45/1266 , H01L45/145 , H01L45/146
Abstract: Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a top electrode, a modulated interfacial region, and a bottom electrode. The thickness of the modulated interfacial region can be modulated between an on state thickness and an off state thickness and the bottom electrode is an active electrode that is a source for metal ions for the creation of a filament between the top electrode and the bottom electrode. In an example, the filament is created when the transistor is in an on state and the filament is not present when the transistor is in an off state.
Abstract translation: 本文公开了用于启用电阻随机存取存储器单元的衬底，组件和技术。 例如，在一些实施例中，器件可以包括顶部电极，调制界面区域和底部电极。 调制的界面区域的厚度可以在开状态厚度和关状态厚度之间进行调节，并且底电极是作为用于在顶电极和底电极之间产生灯丝的金属离子源的活性电极。 在一个例子中，当晶体管处于导通状态时产生灯丝，而当晶体管处于截止状态时灯丝不存在。
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公开(公告)号：WO2018063270A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054615
申请日：2016-09-30
Applicant: INTEL CORPORATION
Inventor： GEORGE, Hubert C. , PILLARISETTY, Ravi , THOMAS, Nicole K. , ROBERTS, Jeanette M. , CLARKE, James S.
CPC classification number: H01L29/122 , H01L29/42356 , H01L29/66469 , H01L29/66977 , H01L29/7613 , H01L29/775 , H01L29/7781 , H01L29/82
Abstract: Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.
Abstract translation: 这里公开的是具有单电子晶体管（SET）检测器的量子点器件。 在一些实施例中，量子点器件可以包括：量子点形成区域; 设置在所述量子点形成区域上的一组栅极，其中所述栅极组至少包括第一栅极，第二栅极和第三栅极，所述第一栅极和所述第二栅极的侧面设置有间隔物，其中第一间隔物设置在所述量子点的一侧 靠近第二栅极的第一栅极和与第一栅极物理分离的第二栅极布置在靠近第一栅极的第二栅极的一侧上，并且第三栅极布置在第一和第二栅极之间并延伸 在第一和第二隔离物之间; 以及设置在量子点形成区域上的SET，靠近该组栅极。
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公开(公告)号：WO2018063202A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054291
申请日：2016-09-29
Applicant: INTEL CORPORATION
Inventor： ROBERTS, Jeanette M. , PILLARISETTY, Ravi , MICHALAK, David J. , YOSCOVITS, Zachary R. , CLARKE, James S. , LE, Van H.
CPC classification number: B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/12 , H01L29/127 , H01L29/165 , H01L29/423 , H01L29/42376 , H01L29/66 , H01L29/66977 , H01L29/80
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a barrier layer and a quantum well layer; gates disposed on the quantum well stack such that the barrier layer is disposed between the gates and the quantum well layer; and strain material regions that extend through the barrier layer and into the quantum well layer. In some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; first gates disposed on the quantum well stack in an array, wherein each first gate has a spacer disposed on either side of the first gate; one or more second gates disposed between adjacent ones of the first gates; and lattice mismatch regions disposed under the spacers, extending into the quantum well layer.
Abstract translation: 这里公开的是量子点器件以及相关的计算设备和方法。 例如，在一些实施例中，量子点器件可以包括：包括势垒层和量子阱层的量子阱堆; 栅极，所述栅极设置在所述量子阱堆叠上，使得所述势垒层设置在所述栅极和所述量子阱层之间; 以及延伸穿过阻挡层并进入量子阱层的应变材料区域。 在一些实施例中，量子点器件可以包括：包括量子阱层的量子阱堆; 以阵列布置在量子阱堆叠上的第一栅极，其中每个第一栅极具有设置在第一栅极的任一侧上的间隔件; 一个或多个第二栅极，设置在相邻的第一栅极之间; 以及位于间隔物下方的晶格失配区域，延伸到量子阱层中。
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公开(公告)号：WO2018057017A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/053608
申请日：2016-09-24
Applicant: INTEL CORPORATION
Inventor： PILLARISETTY, Ravi , ROBERTS, Jeanette M. , THOMAS, Nicole K. , GEORGE, Hubert C. , CLARKE, James S.
IPC: H01L29/775 , H01L29/12 , H01L29/66
Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack with first and second quantum well layers, a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates, a first set of conductive pathways extending from the first set of gates to a first face of the quantum dot device, a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates, and a second set of conductive pathways extending from the second set of gates to a second face of the quantum dot device, wherein the second face is different from the first face.
Abstract translation: 这里公开的是量子点器件以及相关的计算设备和方法。 例如，在一些实施例中，量子点器件可以包括：具有第一和第二量子阱层的量子阱堆，设置在量子阱堆上的第一组栅极，使得第一量子阱层设置在阻挡层 以及所述第一组栅极，从所述第一组栅极延伸到所述量子点器件的第一面的第一组导电路径，设置在所述量子阱堆叠上的第二组栅极，使得所述第二量子阱层被布置 在阻挡层和第二组栅极之间，以及从第二组栅极延伸到量子点器件的第二面的第二组导电路径，其中第二面不同于第一面。
