公开(公告)号：WO2018169538A1

公开(公告)日：2018-09-20

申请号：PCT/US2017/022661

申请日：2017-03-16

Applicant: INTEL CORPORATION

Inventor： BLACKWELL, James M. ,  BRISTOL, Robert L. ,  KRYSAK, Marie ,  EL-MANSY, Mohamed H. ,  LIN, Kevin L. ,  SCHENKER, Richard E. ,  GSTREIN, Florian

IPC: H01L21/027 ,  G03F7/20

CPC classification number: H01L21/31144 ,  H01L21/027 ,  H01L21/311 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76883

Abstract: Photoresists with electron-activated photosensitizers for confined patterning lithography, e.g., for fabricating back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, an integrated circuit structure includes a first layer of an interconnect structure above a substrate, the first layer including a first grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is above the first layer. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. A region of dielectric material is between the metal lines of the first grating and the metal lines of the second grating. The region of dielectric material includes a cross-linked photolyzable material having a bottom and sidewall surfaces lined with a layer including electron-activated photosensitizers.

公开(公告)号：WO2018118092A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068586

申请日：2016-12-23

Applicant: INTEL CORPORATION ,  SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  LIN, Kevin L. ,  GSTREIN, Florian ,  BLACKWELL, James M. ,  KRYSAK, Marie ,  CHANDHOK, Manish ,  NYHUS, Paul A. ,  WALLACE, Charles H. ,  WARD, Curtis W. ,  SIVAKUMAR, Swaminathan ,  TAN, Elliot N.

Inventor： SCHENKER, Richard E. ,  BRISTOL, Robert L. ,  LIN, Kevin L. ,  GSTREIN, Florian ,  BLACKWELL, James M. ,  KRYSAK, Marie ,  CHANDHOK, Manish ,  NYHUS, Paul A. ,  WALLACE, Charles H. ,  WARD, Curtis W. ,  SIVAKUMAR, Swaminathan ,  TAN, Elliot N.

IPC: H01L21/768 ,  H01L21/027

Abstract: Advanced lithography techniques including sub-10nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：WO2018118089A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068582

申请日：2016-12-23

Applicant: INTEL CORPORATION ,  HAN, Eungnak ,  HOURANI, Rami ,  GSTREIN, Florian ,  SINGH, Gurpreet ,  CLENDENNING, Scott B. ,  LIN, Kevin L. ,  CHANDHOK, Manish

Inventor： HAN, Eungnak ,  HOURANI, Rami ,  GSTREIN, Florian ,  SINGH, Gurpreet ,  CLENDENNING, Scott B. ,  LIN, Kevin L. ,  CHANDHOK, Manish

IPC: H01L21/768 ,  H01L21/033

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

公开(公告)号：WO2018063376A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054919

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： LIN, Kevin ,  KASIM, Rahim ,  CHANDHOK, Manish ,  GSTREIN, Florian

IPC: H01L21/768 ,  H01L21/027

CPC classification number: H01L23/5286 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/522 ,  H01L23/5222

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

Abstract translation: 提供了用于在用于高电压应用的半导体管芯的处理期间选择性地去除金属或导电材料的技术。 在一些实施例中，这些技术处理金属化半导体管芯以从沉积在金属化半导体管芯上的图案化光致抗蚀剂层转移特征。 另外，可以对图案化的金属化半导体管芯进行蚀刻工艺以根据图案中的特征去除一定量的金属，从而产生处理过的金属化半导体管芯，该处理后的金属化半导体管芯限定邻近至少一对相邻金属互连 在死亡。 处理后的金属化半导体管芯可以进一步处理以用介电材料回填开口，从而产生具有回填介电部件的金属化半导体管芯。 可以根据记录过程进一步处理这种金属化的半导体管芯，直到金属化，之后可以实施额外的选择性去除另一量的金属。 还提供了具有由回填介电区域分开的相邻金属互连的半导体管芯。

公开(公告)号：WO2017176282A1

公开(公告)日：2017-10-12

申请号：PCT/US2016/026599

申请日：2016-04-08

Applicant: INTEL CORPORATION

Inventor： BRISTOL, Robert L. ,  KRYSAK, Marie ,  BLACKWELL, James M. ,  GSTREIN, Florian ,  FRASURE, Kent N.

IPC: H01L21/027 ,  G03F1/22

CPC classification number: H01L21/31144 ,  G03F7/0045 ,  G03F7/0392 ,  G03F7/203 ,  G03F7/38 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76816

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

Abstract translation: 描述了用于制造后端线路（BEOL）互连的具有可释放猝灭剂的两阶段烘烤光致抗蚀剂。 在一个实例中，可光解组合物包括在波长处具有基本透明性的酸可脱保护的光致抗蚀剂材料，在波长处具有基本透明度的光致酸产生（PAG）组分和在波长处具有基本吸收性的碱产生组分

公开(公告)号：WO2016175782A1

公开(公告)日：2016-11-03

申请号：PCT/US2015/028209

申请日：2015-04-29

Applicant: INTEL CORPORATION ,  CHAWLA, Jasmeet S. ,  HOURANI, Rami ,  KOBRINSKY, Mauro J. ,  GSTREIN, Florian ,  CLENDENNING, Scott B. ,  ROBERTS, Jeanette M.

Inventor： CHAWLA, Jasmeet S. ,  HOURANI, Rami ,  KOBRINSKY, Mauro J. ,  GSTREIN, Florian ,  CLENDENNING, Scott B. ,  ROBERTS, Jeanette M.

IPC: H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1063

Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.

Abstract translation: 可以形成包括导电迹线和导电通孔的导电路径结构，其中导电通孔直接接触导电迹线。 在一个实施例中，可以通过在导电迹线上形成介电材料层来形成导电路径结构。 可以通过介电材料层形成通孔开口以暴露导电迹线的一部分，并且阻挡层可以仅来自导电迹线的暴露部分。 可以在通孔开口的侧壁上形成阻挡线，然后可以去除阻挡层。 然后可以在通孔开口内形成导电通孔，其中导电通孔直接接触导电迹线。

公开(公告)号：WO2016099570A1

公开(公告)日：2016-06-23

申请号：PCT/US2014/071717

申请日：2014-12-19

Applicant: INTEL CORPORATION ,  KLOSTER, Grant ,  CLENDENNING, Scott B. ,  HOURANI, Rami ,  LIAO, Szuya S. ,  ROMERO, Patricio E. ,  GSTREIN, Florian

Inventor： KLOSTER, Grant ,  CLENDENNING, Scott B. ,  HOURANI, Rami ,  LIAO, Szuya S. ,  ROMERO, Patricio E. ,  GSTREIN, Florian

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

Abstract translation: 公开了在半导体结构上选择性地沉积高K栅极电介质的方法。 该方法包括提供设置在半导体衬底之上的半导体结构。 半导体结构设置在隔离侧壁旁边。 牺牲阻挡层然后选择性地沉积在隔离侧壁上，而不是半导体结构上。 此后，高K栅极电介质沉积在半导体结构上，但不沉积在牺牲阻挡层上。 牺牲阻挡层的性质防止氧化物材料在其表面上的沉积。 然后进行热处理以去除牺牲阻挡层，从而仅在半导体结构上形成高K栅极电介质。

公开(公告)号：WO2019005000A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/039364

申请日：2017-06-27

Applicant: INTEL CORPORATION

Inventor： GSTREIN, Florian ,  HOURANI, Rami ,  SAYAN, Safak ,  CHANDHOK, Manish

IPC: H01L21/768 ,  H01L21/02

Abstract: Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings by infiltrating one or more fluid precursors for forming dielectric materials into a solid host matrix provided within the openings. One exemplary method includes providing a host matrix within a plurality of openings in a structure, infiltrating the host matrix within the openings with one or more fluid precursors for forming a dielectric material, and, following the infiltration, removing at least a portion of the host matrix. Assemblies and devices manufactured using such methods are disclosed as well.

公开(公告)号：WO2018125108A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069069

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： KRYSAK, Marie ,  HOURANI, Rami ,  TUFTS, Bruce J. ,  GSTREIN, Florian

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L29/06 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L29/0676 ,  H01L51/00 ,  H01L51/0023 ,  H01L51/0048 ,  H01L2221/1094

Abstract: Disclosed herein are methods for manufacturing devices using nanotubes, such as e.g. carbon nanotubes or boron nitride nanotubes, as a guide for selective deposition of materials. For example, in some embodiments, the methods include growing nanotubes on one or more areas on a surface of a substrate which are referred to herein as "nanotube growth areas," followed by depositing one or more materials over or around the nanotubes and then removing either one or more of the deposited material, or the nanotubes. Assemblies and devices manufactured using such methods are disclosed as well. Such assemblies and devices may advantageously be used in semiconductor ICs.

公开(公告)号：WO2018111289A1

公开(公告)日：2018-06-21

申请号：PCT/US2016/067069

申请日：2016-12-16

Applicant: INTEL CORPORATION

Inventor： BRISTOL, Robert L. ,  LIN, Kevin L. ,  GSTREIN, Florian

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/76885 ,  H01L23/5283

Abstract: Disclosed herein are methods for manufacturing a metallization stack including a plurality of electrically conductive interconnects by subtractive metal spacer based deposition, and related semiconductor devices. For example, in some embodiments, a method of forming a semiconductor device may include providing a pattern of sacrificial elements over an interconnect support layer, depositing an electrically conductive material on sidewalls of the sacrificial elements, and removing the sacrificial elements so that the remaining portions of the electrically conductive material form a pattern of electrically conductive elements which can serve as interconnects of a metallization stack of the semiconductor device.