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公开(公告)号：WO2022076103A1
公开(公告)日：2022-04-14
申请号：PCT/US2021/047987
申请日：2021-08-27
Applicant: INTEL CORPORATION
Inventor： THAKUR, Anshuman , SUBBAREDDY, Dheeraj , HOSSAIN, MD Altaf , NALAMALPU, Ankireddy , KUMASHIKAR, Mahesh
Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.
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公开(公告)号：WO2021055131A1
公开(公告)日：2021-03-25
申请号：PCT/US2020/047063
申请日：2020-08-19
Applicant: INTEL CORPORATION
Inventor： LIU, Huichu , KARNIK, Tanay , SINGH, Tejpal , LIU, Yen-Cheng , SUBRAMANIAN, Lavanya , KUMASHIKAR, Mahesh , CHODAY, Sri Harsha , SUBRAMONEY, Sreenivas , VAIDYANATHAN, Kaushik , MORRIS, Daniel H. , AVCI, Uygar E. , YOUNG, Ian A.
IPC: H04L12/937 , H04L12/935 , H04L12/931 , H04L12/841 , H04L12/10
Abstract: Described is an low overhead method and apparatus to reconfigure a pair of buffered interconnect links to operate in one of these three modes-first mode (e.g., bandwidth mode), second mode (e.g., latency mode), and third mode (e.g., energy mode). In bandwidth mode, each link in the pair buffered interconnect links carries a unique signal from source to destination. In latency mode, both links in the pair carry the same signal from source to destination, where one link in the pair is "primary" and other is called the "assist". Temporal alignment of transitions in this pair of buffered interconnects reduces the effective capacitance of primary, thereby reducing delay or latency. In energy mode, one link in the pair, the primary, alone carries a signal, while the other link in the pair is idle. An idle neighbor on one side reduces energy consumption of the primary.
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公开(公告)号：WO2019054998A1
公开(公告)日：2019-03-21
申请号：PCT/US2017/051320
申请日：2017-09-13
Applicant: INTEL CORPORATION , THOMAS, Thomas P. , GOMES, Wilfred , MAHAJAN, Ravindranath V. , KUMAR, Rajesh , BOHR, Mark T. , SUBBAREDDY, Dheeraj , NALAMALPU, Ankireddy , KUMASHIKAR, Mahesh
Inventor： THOMAS, Thomas P. , GOMES, Wilfred , MAHAJAN, Ravindranath V. , KUMAR, Rajesh , BOHR, Mark T. , SUBBAREDDY, Dheeraj , NALAMALPU, Ankireddy , KUMASHIKAR, Mahesh
IPC: H01L25/065 , H01L23/538
Abstract: A package substrate and a package assembly including a package substrate including a substrate body including a plurality of first contact points on a surface thereof configured for electrical connection to a first die and a plurality of second contact points on the surface configured for electrical connection to a second die; and a bridge coupled to the substrate body, the bridge including active device circuitry that is coupled to ones of the plurality of first contact points and ones of the plurality of second contact points. A method of forming a package assembly including coupling a first die to a package substrate, the package substrate including a bridge substrate including active device circuitry; and coupling a second die to the package substrate, wherein coupling the first die and the second die to the package substrate includes coupling the first die and the second die to the active circuitry.
