公开(公告)号：WO2018004799A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/029166

申请日：2017-04-24

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

IPC: H01L23/482 ,  H01L23/538 ,  H01L23/043 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4857 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13155 ,  H01L2224/13599 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/15192

Abstract: Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes a substrate; a silicon interconnect bridge including a plurality of interconnections, the interconnect bridge being embedded in the substrate; and a plurality of contacts on a surface of the substrate, the plurality of contacts being coupled with the plurality of interconnections of the interconnect bridge. The interconnect bridge is bonded in a cavity in the substrate, the cavity being formed by removal of at least one temporary structure from the substrate.

Abstract translation: 实施例通常针对利用临时结构的嵌入互连桥的腔生成。 封装的实施例包括衬底; 包括多个互连的硅互连桥，所述互连桥嵌入在所述衬底中; 以及在所述衬底的表面上的多个触点，所述多个触点与所述互连桥的所述多个互连耦合。 互连桥结合在衬底中的空腔中，空腔通过从衬底去除至少一个临时结构而形成。

公开(公告)号：WO2022108647A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/049666

申请日：2021-09-09

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  PAITAL, Sameer ,  VADLIMANI, Sai ,  MANEPALLI, Rahul N. ,  LI, Xiaoqian ,  POTHUKUCHI, Suresh V. ,  SHARAN, Sujit ,  SARKAR, Arnab ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PRATAP, Divya ,  ECTON, Jeremy ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ZHANG, Zhichao ,  AYGÜN, Kemal ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  JAUSSI, James E. ,  GAMBA, Jason M. ,  CASPER, Bryan K. ,  DUAN, Gang ,  INTI, Rajesh ,  MANSURI, Mozhgan ,  JADHAV, Susheel ,  BROWN, Kenneth ,  AGRAWAL, Ankar ,  DOBRIYAL, Priyanka

IPC: G02B6/42 ,  H01L31/0203 ,  H01L23/538 ,  H01L25/16

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：WO2018182595A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/024780

申请日：2017-03-29

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N. ,  AKKINEPALLY, Praneeth ,  JONES, Jesse C. ,  KANAOKA, Yosuke ,  SENEVIRATNE, Dilan

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/67

Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：WO2017172281A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020986

申请日：2017-03-06

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

IPC: H01L21/48 ,  H01L23/538

Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

Abstract translation: 公开了电互连桥技术。 电互连桥可以包括由模制复合材料形成的桥基板。 电互连桥还可以包括桥衬底内的多个布线层，每个布线层具有多个细线和空间（FLS）迹线。 另外，电互连桥可以包括延伸穿过衬底的通孔并且将一个布线层中的至少一个FLS迹线电耦合到另一个布线层中的至少一个FLS迹线。

公开(公告)号：WO2018182653A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025200

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N. ,  DARMAWIKARTA, Kristof Kuwawi ,  MAY, Robert Alan ,  ALEKSOV, Aleksandar ,  KAMGAING, Telesphor

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/485 ,  H01L23/00

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.

公开(公告)号：WO2017112223A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/063161

申请日：2016-11-21

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

IPC: H01L23/29 ,  H01L21/56

CPC classification number: B32B27/20 ,  B32B27/06 ,  B32B27/38 ,  B32B2457/00 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/145 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18

Abstract: This document discusses, among other things, a microelectronic system including a mold compound having a base layer and a surface layer on the base layer, and a seed layer deposited on the surface layer of the mold compound. The mold compound includes a monomer epoxy resin, a hardener, a filler material, and a polymer interphase material, wherein the polymer interphase material forms the surface layer of the mold compound having an adhesion strength to the seed layer greater than the monomer epoxy resin and hardener alone.

Abstract translation: 该文献尤其讨论了一种微电子系统，该微电子系统包括在基层上具有基层和表面层的模塑复合物，以及沉积在模塑复合物的表面层上的晶种层。 所述模塑料包括单体环氧树脂，硬化剂，填充材料和聚合物中间相材料，其中所述聚合物中间层材料形成比所述单体环氧树脂更大的与所述种子层的粘合强度的所述模塑料的表面层，以及 单独的硬化剂。

公开(公告)号：WO2017087069A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/053400

申请日：2016-09-23

Applicant: INTEL CORPORATION

Inventor： ALEKSOV, Aleksandar ,  PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

IPC: H04M1/02 ,  H01Q1/24

CPC classification number: H05K1/184 ,  H05K1/0283 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/185 ,  H05K3/007 ,  H05K3/4697 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/0191 ,  H05K2203/1469

Abstract: An embedded electronic package includes a stretchable body that includes at least one electronic component, wherein each electronic component includes a back side that is exposed from the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components. In some forms, the embedded electronic package includes a stretchable body that includes an upper surface and a lower surface, wherein the stretchable body includes at least one electronic component, wherein each electronic component is fully embedded in the stretchable body and the same distance from the upper surface of the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components.

Abstract translation: 嵌入式电子组件包括：包括至少一个电子部件的可拉伸体，其中每个电子部件包括从可拉伸体暴露的后侧; 以及电连接到一个或多个电子部件的多个曲折导体。 在一些形式中，嵌入式电子组件包括包括上表面和下表面的可拉伸主体，其中，可拉伸主体包括至少一个电子部件，其中每个电子部件完全嵌入可拉伸主​​体中，并且距离 伸缩体的上表面; 以及电连接到一个或多个电子部件的多个曲折导体。

公开(公告)号：WO2018125166A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069321

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： JAIN, Rahul ,  LEE, Kyu Oh ,  ALUR, Siddharth K. ,  JEN, Wei-Lun K. ,  MEHTA, Vipul V. ,  DHALL, Ashish ,  CHAVALI, Sri Chaitra J. ,  MANEPALLI, Rahul N. ,  ALUR, Amruthavalli P. ,  VADLAMANI, Sai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/525 ,  H01L23/538 ,  H01L23/12 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2017146737A1

公开(公告)日：2017-08-31

申请号：PCT/US2016/019943

申请日：2016-02-26

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

IPC: H01L23/48

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345

Abstract: Embodiments herein may relate to providing, on a pad coupled with a carrier panel, a sacrificial element. Embodiments may further relate to providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. Embodiments may further relate to removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad. Other embodiments may be described and/or claimed.

Abstract translation: 这里的实施例可以涉及在与载体面板耦合的焊盘上提供牺牲元件。 实施例还可以涉及在垫上提供模制化合物，其中模制化合物至少部分地邻近牺牲元件。 实施例还可以涉及在提供模制化合物之后去除牺牲元件以在模制化合物中形成通孔以至少部分地暴露垫。 其他实施例可以被描述和/或要求保护。

公开(公告)号：WO2017105388A1

公开(公告)日：2017-06-22

申请号：PCT/US2015/065511

申请日：2015-12-14

Applicant: INTEL CORPORATION

Inventor： MAY, Robert Alan ,  DARMAWIKARTA, Kristof ,  JAIN, Rahul ,  BOYAPATI, Sri Ranga Sai ,  MOUSSALLEM, Maroun ,  MANEPALLI, Rahul N. ,  PIETAMBARAM, Srinivas

IPC: G02B6/132

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/134

Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.

Abstract translation: 该文献尤其讨论了一种波导，该波导包括第一金属和第二金属，该第一金属具有接近介电材料的外表面和限定波导的路径的内表面，在该接收器处接收光信号的方法 所述波导的内表面并且沿着所述波导的所述路径的至少一部分传输所述光信号。 一种将波导集成在衬底中的方法包括在载体衬底的第一表面上沉积牺牲金属以形成波导的核心，在牺牲金属上沉积第一金属以及载体衬底的第一表面的至少一部分 ，形成波导的外表面和与牺牲金属分开的导体，并且在载体衬底的第一表面上围绕导体沉积介电材料。