公开(公告)号：WO2017074391A1

公开(公告)日：2017-05-04

申请号：PCT/US2015/058072

申请日：2015-10-29

Applicant: INTEL CORPORATION

Inventor： SARKAR, Arnab ,  SHARAN, Sujit ,  KIM, Dae-Woo

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/14 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

Abstract translation: 描述了保护环设计，其能够在线测试用于半导体封装的硅桥以及由此产生的硅桥和半导体封装。 在一个示例中，半导体结构包括其上设置有绝缘层的衬底。 金属化结构设置在绝缘层上。 金属化结构包括设置在电介质材料堆叠中的导电布线。 半导体结构还包括设置在介电材料堆叠中并且围绕导电布线的第一金属保护环。 第一金属保护环包括多个单独的保护环段。 半导体结构还包括设置在介电材料堆叠中并且围绕第一金属保护环的第二金属保护环。 电气测试特征设置在介电材料叠层中，在第一金属保护环和第二金属保护环之间。

公开(公告)号：WO2017111825A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000383

申请日：2015-12-26

Applicant: INTEL CORPORATION

Inventor： SARKAR, Arnab ,  MAHAJAN, Ravindranath, V.

IPC: H01L25/16 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: Embodiments are generally directed to hybrid technology 3-D die stacking. An embodiment of an apparatus includes a TSV array substrate including through silicon vias (TSVs) and wire bond contacts; a stack of one or more wire bond dies; and a package coupled with the TSV substrate by a first interconnect, wherein the one or more wire bond dies are connected via one or more wires to one or more wire bond contacts of the TSV array substrate, and wherein the TSV array substrate provides connections to the for each of the one or more wire bond dies.

Abstract translation: 实施例通常针对混合技术3-D芯片堆叠。 一种设备的实施例包括：TSV阵列基板，其包括硅通孔（TSV）和引线接合触点; 一个或多个引线接合管芯的堆叠; 以及通过第一互连与所述TSV衬底耦合的封装，其中所述一个或多个引线接合裸片经由一个或多个引线连接到所述TSV阵列衬底的一个或多个引线接合触点，并且其中所述TSV阵列衬底提供与 用于一个或多个引线键合管芯中的每一个。

公开(公告)号：WO2022108647A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/049666

申请日：2021-09-09

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  PAITAL, Sameer ,  VADLIMANI, Sai ,  MANEPALLI, Rahul N. ,  LI, Xiaoqian ,  POTHUKUCHI, Suresh V. ,  SHARAN, Sujit ,  SARKAR, Arnab ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PRATAP, Divya ,  ECTON, Jeremy ,  MALLIK, Debendra ,  MAHAJAN, Ravindranath V. ,  ZHANG, Zhichao ,  AYGÜN, Kemal ,  NIE, Bai ,  DARMAWIKARTA, Kristof ,  JAUSSI, James E. ,  GAMBA, Jason M. ,  CASPER, Bryan K. ,  DUAN, Gang ,  INTI, Rajesh ,  MANSURI, Mozhgan ,  JADHAV, Susheel ,  BROWN, Kenneth ,  AGRAWAL, Ankar ,  DOBRIYAL, Priyanka

IPC: G02B6/42 ,  H01L31/0203 ,  H01L23/538 ,  H01L25/16

Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：WO2019066977A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054638

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： ALEKSOV, Aleksandar ,  STRONG, Veronica ,  DARMAWIKARTA, Kristof ,  SARKAR, Arnab

IPC: H01L23/522 ,  H01L23/498

Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.