公开(公告)号：WO2018132653A1

公开(公告)日：2018-07-19

申请号：PCT/US2018/013484

申请日：2018-01-12

Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

Inventor： MOUDGILL, Mayan ,  HOANE, A. Joseph ,  WANG, Lei ,  NACER, Gary ,  MILBURY, Aaron G. ,  BARRIA, Enrique A. ,  HURTLEY, Paul

IPC: G06F9/26 ,  G06F9/34

Abstract: A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual, memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.