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1.发明申请公开(公告)号：WO2022005629A1
公开(公告)日：2022-01-06
申请号：PCT/US2021/032308
申请日：2021-05-13
Applicant: QUALCOMM INCORPORATED
Inventor： BAKHSHIANI, Mehran , LAKDAWALA, Hasnain , ABBAS MOHAMED HELMY, Ahmed , KARMAKER, Rahul , GUHADOS, Shankar , GATTA, Francesco
IPC: H03H11/12 , H03H11/04 , H04B1/10 , H03F2200/129 , H03F2200/165 , H03F2203/45526 , H03F3/45475 , H03G3/30 , H03H11/1217 , H03H11/1226 , H03H11/1291 , H03H19/004 , H03H2011/0483 , H03H2011/0494 , H04B1/0032 , H04B1/0039 , H04B1/0042 , H04B1/0078 , H04B1/1615 , H04B1/18
Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.
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公开(公告)号：WO2023048981A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/043228
申请日：2022-09-12
Applicant: QUALCOMM INCORPORATED
Inventor： ABBAS MOHAMED HELMY, Ahmed , GATTA, Francesco , RAMACHANDRAN, Balasubramanian , KULKARNI, Abhishek Ananthrao , THOPPAY EGAMBARAM, Prakash , LAKDAWALA, Hasnain , TASIC, Aleksandar Miodrag , LEE, Jang Joon , HOLLAND, Kyle David
Abstract: Certain aspects of the present disclosure generally relate to techniques and apparatus for operating a wireless receiver of the apparatus in a high linearity mode. An example method includes operating the apparatus in a first mode with transmission of a plurality of transmit signals. The method also includes attenuating a received signal via an attenuator while operating the apparatus in the first mode. The method further includes amplifying the attenuated signal with an amplifier while operating the apparatus in the first mode. For certain aspects, the method further involves operating the apparatus in a second mode, bypassing the attenuator while operating the apparatus in the second mode, and amplifying the received signal with the amplifier while operating the apparatus in the second mode.
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公开(公告)号：WO2022132401A2
公开(公告)日：2022-06-23
申请号：PCT/US2021/060374
申请日：2021-11-22
Applicant: QUALCOMM INCORPORATED
Inventor： LEUNG, Lai Kan , TASIC, Aleksandar Miodrag , GATTA, Francesco , NARATHONG, Chiewcharn , HOLLAND, Kyle David
IPC: H04B1/10 , H03F2200/294 , H03F2200/451 , H03F3/19 , H03M1/12 , H04B1/1027 , H04B1/109 , H04K3/22
Abstract: The disclosure relates to an apparatus including a receiver configured to process a radio frequency (RF) signal to generate a baseband signal; a radio frequency (RF) jammer detector configured to generate a signal indicative of whether an RF jammer is present at an input of the receiver; and a receiver bias circuit configured to generate a supply voltage for the receiver based on the RF jammer indication signal. In another aspect, the apparatus includes constant gain bias circuit to maintain the gain of the receiver constant in response to changes in the supply voltage. In other aspects, the receiver bias circuit may suspend the generating of the supply voltage based on the RF jammer indication signal if the power level of the target received signal is above a threshold. In other aspects, the receiver bias circuit changes the supply voltage during cyclic prefix (CP) intervals between downlink intervals.
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4.发明申请
公开(公告)号：WO2021262613A1
公开(公告)日：2021-12-30
申请号：PCT/US2021/038298
申请日：2021-06-21
Applicant: QUALCOMM INCORPORATED
Inventor： GOPAL, Thawatt , CHEN, Qingxin , SHAHIDI, Reza , GATTA, Francesco
IPC: H04W52/14 , H04W52/16 , H04W52/36 , H04W52/146 , H04W52/346 , H04W52/367 , H04W52/52
Abstract: Apparatus, methods, and computer-readable media for facilitating managing multi-SIM concurrent mode for TDD co-banded or spectrum overlap carriers are disclosed herein. An example method for wireless communication at a user equipment (UE) includes estimating a maximum transmit power for a first subscriber based on a low-noise amplifier (LNA) input power threshold associated with an active receive chain of a second subscriber, where the UE comprises the first subscriber and the second subscriber. The example method also includes transmitting, via an active transmit chain of the first subscriber, an uplink transmission at the first subscriber maximum transmit power based on the first subscriber and the second subscriber operating concurrently, and a transmit power associated with the uplink transmission being greater than the first subscriber maximum transmit power.
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公开(公告)号：WO2022203860A1
公开(公告)日：2022-09-29
申请号：PCT/US2022/019405
申请日：2022-03-08
Applicant: QUALCOMM INCORPORATED
Inventor： MEDRA, Alaaeldien Mohamed Abdelrazek , GATTA, Francesco
Abstract: A wideband amplifier includes a first stage and a second stage. The first stage includes a transconductance transistor driven by an input signal through an input transformer. The transconductance transistor couples to a cascode transistor forming an output node for the first stage. The second stage couples the output node from the first stage through an output transformer to drive an output transistor.
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公开(公告)号：WO2020112283A1
公开(公告)日：2020-06-04
申请号：PCT/US2019/058070
申请日：2019-10-25
Applicant: QUALCOMM INCORPORATED
Inventor： MEDRA, Alaaeldien Mohamed Abdelrazek , YANG, David Zixiang , WANG, Kevin Hsi Huai , ZHAI, Chen , GATTA, Francesco
Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.
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公开(公告)号：WO2017204902A1
公开(公告)日：2017-11-30
申请号：PCT/US2017/025547
申请日：2017-03-31
Applicant: QUALCOMM INCORPORATED
Inventor： ZANUSO, Marco , ELBADRY, Mohammad , HUNG, Tsai-Pi , SRIDHARA, Ravi , GATTA, Francesco , ZHUANG, Jingcheng
IPC: H03L7/14
CPC classification number: H04L7/033 , H03L7/14 , H03L7/143 , H03L7/1976 , H03L2207/08 , H04L5/14 , H04L69/28 , H04W84/042
Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.
Abstract translation: 相位锁定环（PLL）内的相位不连续性缓解实现提高了无线电接入技术的吞吐量。 在断开PLL的一些器件（如本地振荡器（LO）分频器）时，通过保持PLL的相位来改善吞吐量。 在一个实例中，当PLL断电时，PLL的一个或多个部分的Δ-Σ调制器以PLL的参考时钟为时钟。 当第一个锁相环打开时，此实现可保持相位连续性。
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公开(公告)号：WO2023048982A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/043235
申请日：2022-09-12
Applicant: QUALCOMM INCORPORATED
Inventor： LAKDAWALA, Hasnain , ABBAS MOHAMED HELMY, Ahmed , GATTA, Francesco , RAMACHANDRAN, Balasubramanian , HUMNABADKAR, Ketan , FENAROLI, Andrea
Abstract: Techniques and apparatus are described for reducing power consumption when performing wireless communications by dynamically changing the frequency of a local oscillator signal for a radio frequency (RF) downconversion circuit, based on signal conditions. An example method includes receiving an RF signal and downconverting the RF signal using an oscillating signal with a first frequency at a first time. The method also includes switching to downconverting the RF signal using the oscillating signal with a second frequency, based on a property associated with the RF signal at a second time. The second frequency is a subharmonic of the first frequency.
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9.发明申请
公开(公告)号：WO2022005630A1
公开(公告)日：2022-01-06
申请号：PCT/US2021/032310
申请日：2021-05-13
Applicant: QUALCOMM INCORPORATED
Inventor： ABBAS MOHAMED HELMY, Ahmed , BAKHSHIANI, Mehran , GATTA, Francesco
IPC: H03H11/12 , H04B1/10 , H03H11/04 , H03F2200/129 , H03F2200/165 , H03F2203/45526 , H03F3/45475 , H03G3/30 , H03H11/1217 , H03H11/1226 , H03H11/1291 , H03H19/004 , H03H2011/0483 , H03H2011/0494 , H04B1/0032 , H04B1/0039 , H04B1/0042 , H04B1/0078 , H04B1/1615 , H04B1/18
Abstract: An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and merging at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.
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公开(公告)号：WO2017189160A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/025171
申请日：2017-03-30
Applicant: QUALCOMM INCORPORATED
Inventor： ZANUSO, Marco , MARUCCI, Giovanni , HUNG, Tsai-Pi , GATTA, Francesco , SUN, Bo
CPC classification number: H04L7/0331 , H03L7/08 , H03L7/087 , H03L7/099 , H03L7/113 , H03L7/1974 , H03L7/1976 , H03L2207/06 , H04B1/40 , H04B1/713 , H04B2201/71353 , H04W72/0453
Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.
Abstract translation: 锁相环（PLL）电路中的快速跳频实现在很短的时间内实现了PLL锁定到新的频率。 在一个瞬间，收发器处的频率分配被改变。 作为响应，基于改变的频率分配，本地振荡器频率跳跃到新的中心频率。 跳到新的中心频率是基于锁相环的两点调制。
