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    TABLE LOOKUP USING SIMD INSTRUCTIONS
    2.
    发明申请
    TABLE LOOKUP USING SIMD INSTRUCTIONS 审中-公开
    表使用SIMD指令

    公开(公告)号：WO2017030675A1

    公开(公告)日：2017-02-23

    申请号：PCT/US2016/041698

    申请日：2016-07-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： MAHURIN, Eric Wayne ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  HOYLE, David ,  ZENG, Mao ,  GAN, Kim-Chyan

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/30003 ,  G06F9/3004

    Abstract: Systems and methods pertain to looking up entries of a table. A processor receives one or more single instruction multiple data (SIMD) instructions, including a first SIMD instruction which specifies a first subset of indices. A first subset of table entries is looked up, using a crossbar, with the first subset of indices. A first vector output of the first SIMD instruction is based on whether the outputs of the crossbar belong to a desired subset of table entries. Similarly, second, third, and fourth SIMD instructions specify corresponding second, third, and fourth subsets of indices to lookup the remaining table entries using the crossbar. The size of the crossbar is based on the number of indices in the subset of indices used to lookup table entries.

    Abstract translation: 系统和方法属于查找表的条目。 处理器接收一个或多个单指令多数据（SIMD）指令，包括指定索引的第一子集的第一SIMD指令。 使用交叉开关查找表条目的第一个子集，并使用索引的第一个子集。 第一SIMD指令的第一矢量输出基于交叉开关的输出是否属于表条目的期望子集。 类似地，第二，第三和第四SIMD指令指定相应的第二，第三和第四索引子集，以使用横杠来查找剩余的表条目。 交叉开关的大小基于用于查找表条目的索引子集中的索引数。

    INSERTING A PROXY READ INSTRUCTION IN AN INSTRUCTION PIPELINE IN A PROCESSOR
    3.
    发明申请
    INSERTING A PROXY READ INSTRUCTION IN AN INSTRUCTION PIPELINE IN A PROCESSOR 审中-公开

    公开(公告)号：WO2022031543A1

    公开(公告)日：2022-02-10

    申请号：PCT/US2021/043943

    申请日：2021-07-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： MAHURIN, Eric Wayne ,  RADAIDEH, Ahmad Mahmoud

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/30141 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3836

    Abstract: Inserting a proxy read instruction in an instruction pipeline in a processor is disclosed. A scheduler circuit is configured to recognize when a produced value generated by execution of a producer instruction in the instruction pipeline will not be available through a data forwarding path to be consumed for processing of a subsequent consumer instruction. In this case, the scheduling circuit is configured to insert a proxy read instruction in the instruction pipeline to cause execution of an operation to generate the same produced value as was generated by previous execution of producer instruction in the instruction pipeline. Thus, the produced value will remain available in the instruction pipeline to again be available through a data forwarding path to an earlier stage of the instruction pipeline to be consumed by a consumer instruction, which may avoid a pipeline stall.

    METHOD AND APPARATUS FOR PERFORMING SIMD GATHER AND COPY OPERATIONS
    5.
    发明申请
    METHOD AND APPARATUS FOR PERFORMING SIMD GATHER AND COPY OPERATIONS 审中-公开
    用于执行SIMD收集和复制操作的方法和设备

    公开(公告)号：WO2017222798A1

    公开(公告)日：2017-12-28

    申请号：PCT/US2017/036041

    申请日：2017-06-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： MAHURIN, Eric Wayne ,  GOLAB, Jakub Pawal ,  CODRESCU, Lucian

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F12/00

    Abstract: Systems and methods relate to efficient memory operations. A single instruction multiple data (SIMD) gather operation is implemented with a gather result buffer located within or in close proximity to memory, to receive or gather multiple data elements from multiple orthogonal locations in a memory, and once the gather result buffer is complete, the gathered data is transferred to a processor register. A SIMD copy operation is performed by executing two or more instructions for copying multiple data elements from multiple orthogonal source addresses to corresponding multiple destination addresses within the memory, without an intermediate copy to a processor register. Thus, the memory operations are performed in a background mode without direction by the processor.

    Abstract translation: 系统和方法涉及有效的存储器操作。 利用位于存储器内或紧邻存储器的收集结果缓冲器来实现单指令多数据（SIMD）收集操作，以从存储器中的多个正交位置接收或收集多个数据元素，并且一旦收集结果缓冲器完成， 收集的数据被传送到处理器寄存器。 SIMD复制操作通过执行两个或更多指令来执行，用于将多个正交源地址的多个数据元素复制到存储器内的相应的多个目的地地址，而不需要中间复制到处理器寄存器。 因此，存储器操作在处理器没有指示的背景模式下执行。

    SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS
    6.
    发明申请
    SIMD MULTIPLY AND HORIZONTAL REDUCE OPERATIONS 审中-公开
    SIMD MULTIPLY和水平减少操作

    公开(公告)号：WO2017030676A1

    公开(公告)日：2017-02-23

    申请号：PCT/US2016/041717

    申请日：2016-07-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： MAHURIN, Eric Wayne

    IPC: G06F17/16 ,  G06F9/00

    CPC classification number: G06F9/3001 ,  G06F9/30036 ,  G06F17/16

    Abstract: Systems and methods relate to multiply-and-horizontal-reduce operations, implemented in a digital filter, for example. A single instruction multiple data (SIMD) instruction comprising a first vector comprising M + C multiplicand elements, wherein M and C are positive integers and a second vector comprising M + C corresponding multiplier elements, wherein the C multiplier elements have a value of 1, is received. Using M multipliers in a processor, M multiplications of M multiplicand elements with corresponding M multiplier elements which do not include the C multiplier elements whose values are 1, are performed to generate M products. The C multiplicand elements whose corresponding C multiplier elements have values of 1 are added to or vertically accumulated with the M products.

    Abstract translation: 例如，系统和方法涉及在数字滤波器中实现的乘法和水平减少运算。 一种单指令多数据（SIMD）指令，包括包含M + C个被乘数的第一向量，其中M和C是正整数，以及包括M + C对应的乘法器元件的第二向量，其中C乘法器元件具有值1， 被收到。 在处理器中使用M个乘法器，执行M个被乘数元素与不包括其值为1的C个乘法器元素的相应M个乘法器元素的M个乘法，以产生M个乘积。 其对应的C乘数元素具有值1的C个被乘数元素被添加到M个乘积或垂直累积。

    HYBRID CONVOLUTION OPERATION
    7.
    发明申请
    HYBRID CONVOLUTION OPERATION 审中-公开

    公开(公告)号：WO2021158631A1

    公开(公告)日：2021-08-12

    申请号：PCT/US2021/016373

    申请日：2021-02-03

    Applicant: QUALCOMM INCORPORATED

    Inventor： MAHURIN, Eric Wayne

    IPC: G06T1/20

    Abstract: A device includes one or more processors configured to retrieve a first block of data, the data corresponding to array of values arranged along at least a first dimension and a second dimension, to retrieve at least a portion of a second block of the data, and to perform a first hybrid convolution operation that applies a filter across the first block and at least the portion of the second block to generate output data. The output data includes a first accumulated block and at least a portion of a second accumulated block. The one or more processors are also configured to store the first accumulated block as first output data. The portion of the second block is adjacent to the first block along the first dimension and the portion of the second accumulated block is adjacent to the first accumulated block along the second dimension.

    CONTROLLING VOLTAGE DEVIATIONS IN PROCESSING SYSTEMS
    9.
    发明申请
    CONTROLLING VOLTAGE DEVIATIONS IN PROCESSING SYSTEMS 审中-公开
    控制处理系统中的电压偏差

    公开(公告)号：WO2017053078A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/050767

    申请日：2016-09-08

    Applicant: QUALCOMM INCORPORATED

    Inventor： MAHURIN, Eric Wayne ,  PATIL, Sanjay Bhagawan ,  SAINT-LAURENT, Martin Pierre

    IPC: G06F1/32

    CPC classification number: G06F1/26 ,  G06F1/3206 ,  G06F1/329 ,  Y02D10/24

    Abstract: Systems and methods relate to controlling voltage deviations in processing systems. A scheduler receives transactions and to be issued for execution in a pipeline. A voltage deviation that will occur if a particular transaction is executed in the pipeline is estimated before the transaction is issued. Threshold comparators are used to determine if the estimated voltage deviation will exceed specified thresholds to cause voltage overshoots or undershoots. The scheduler is configured to implement one or more corrective measures, such as increasing or decreasing energy in the pipeline, to mitigate possible voltage overshoots or undershoots, before the transaction is issued to be executed in the pipeline.

    Abstract translation: 系统和方法涉及控制处理系统中的电压偏差。 调度器接收事务并发布以便在管道中执行。 在交易发出之前，估计在流水线中执行特定事务时将发生的电压偏差。 阈值比较器用于确定估计的电压偏差是否超过指定的阈值以引起电压过冲或欠冲。 调度器被配置为在事务被发布以在流水线中执行之前实现一个或多个校正措施，例如增加或减少流水线中的能量，以减轻可能的电压过冲或欠冲击。

    MIXED-WIDTH SIMD OPERATIONS HAVING EVEN-ELEMENT AND ODD-ELEMENT OPERATIONS USING REGISTER PAIR FOR WIDE DATA ELEMENTS
    10.
    发明申请
    MIXED-WIDTH SIMD OPERATIONS HAVING EVEN-ELEMENT AND ODD-ELEMENT OPERATIONS USING REGISTER PAIR FOR WIDE DATA ELEMENTS 审中-公开
    使用寄存器对进行数据元素的混合宽度SIMD操作具有即时元素和空白元素操作

    公开(公告)号：WO2017014892A1

    公开(公告)日：2017-01-26

    申请号：PCT/US2016/038487

    申请日：2016-06-21

    Applicant: QUALCOMM INCORPORATED

    Inventor： MAHURIN, Eric Wayne ,  INGLE, Ajay Anant

    IPC: G06F9/30

    CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30098 ,  G06F9/30109 ,  G06F9/30112

    Abstract: Systems and methods relate to a mixed-width single instruction multiple data (SIMD) instruction which has at least a source vector operand comprising data elements of a first bit-width and a destination vector operand comprising data elements of a second bit-width, wherein the second bit-width is either half of or twice the first bit-width. Correspondingly, one of the source or destination vector operands is expressed as a pair of registers, a first register and a second register. The other vector operand is expressed as a single register. Data elements of the first register correspond to even-numbered data elements of the other vector operand expressed as a single register, and data elements of the second register correspond to data elements of the other vector operand expressed as a single register.

    Abstract translation: 系统和方法涉及混合宽度单指令多数据（SIMD）指令，其具有至少包括第一位宽的数据元素和包含第二位宽的数据元素的目的地向量操作数的源向量操作数，其中 第二个位宽是第一个位宽的一半或两倍。 相应地，源或目标向量操作数之一被表示为一对寄存器，第一寄存器和第二寄存器。 另一个向量操作数表示为单个寄存器。 第一寄存器的数据元素对应于表示为单个寄存器的另一向量操作数的偶数数据元，第二寄存器的数据元对应于表示为单个寄存器的另一向量操作数的数据元。

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