-
公开(公告)号：WO2014138048A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/020276
申请日：2014-03-04
Applicant: QUALCOMM INCORPORATED
Inventor： PANDEY, Shree Krishna , SUN, Changyu
CPC classification number: G06F17/5036 , G06F17/5068 , G06F17/5077 , G06F17/5081 , G06F2217/82 , G11C5/005 , G11C5/063
Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generate a plurality of interconnect patterns for a set of vertical interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of vertical interconnects within a predefined area of a substrate in the semiconductor device. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. One or more sets of interconnects is formed on a substrate in accordance with the preferred pattern. At least one set of interconnects may be rotated with respect to another set of interconnects on the substrate to minimize crosstalk between the sets of interconnects.
Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 该装置为一组垂直互连产生多个互连图案。 每个互连图案可以不同于其他互连图案。 每个互连图案可以限定半导体器件中的衬底的预定区域内的垂直互连组的相对位置。 对于每个互连图案确定最高串扰，并且选择具有最小最高串扰的互连图案作为优选图案。 根据优选图案在基板上形成一组或多组互连。 至少一组互连可以相对于衬底上的另一组互连旋转，以最小化互连组之间的串扰。
-
公开(公告)号：WO2017180281A1
公开(公告)日：2017-10-19
申请号：PCT/US2017/022368
申请日：2017-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： PANDEY, Shree Krishna , KUNDU, Arun Chandra , WILEY, George Alan , LEE, Chulkyu
IPC: H04L25/02
CPC classification number: H04L25/0272 , H04B3/46 , H04L25/02 , H04L25/0292 , H04L25/0298
Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.
Abstract translation: 在包括至少三根导线的多导线通道中，多导线通道的每对唯一导线对具有大致相同的信号传播时间。 通过这种方式，可以在多线信道中缓解抖动，用于发送信号，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每个其他导线都是浮动的。 在一些实现中，信号传播时间的匹配涉及为至少一个导线提供附加延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供附加延迟。
-
3.发明申请INTEGRATED DEVICE COMPRISING A CAPACITOR THAT INCLUDES MULTIPLE PINS AND AT LEAST ONE PIN THAT TRAVERSES A PLATE OF THE CAPACITOR 审中-公开包含电容器的集成器件，该电容器包括多个引脚并且至少一个引脚穿过电容器板
公开(公告)号：WO2017139410A1
公开(公告)日：2017-08-17
申请号：PCT/US2017/017059
申请日：2017-02-08
Applicant: QUALCOMM INCORPORATED
Inventor： GU, Shiqun , PANDEY, Shree Krishna , RADOJCIC, Ratibor
IPC: H01L23/64 , H01L23/498 , H01L23/538 , H01L21/60 , H01L49/02
CPC classification number: H01L23/49838 , H01L21/4846 , H01L21/568 , H01L23/3128 , H01L23/49822 , H01L23/5389 , H01L23/642 , H01L24/17 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16238 , H01L2224/16268 , H01L2224/18 , H01L2924/05042 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19102
Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.
Abstract translation: 一些特征涉及包括管芯和耦合到管芯的第一重新分配部分的集成器件。 第一重新分配部分包括至少一个介电层和电容器。 电容器包括第一板，第二板以及位于第一板和第二板之间的绝缘层。 第一重新分配部分还包括耦合到电容器的第一板的多个第一引脚。 第一重新分配部分还包括耦合到电容器的第二板的若干第二引脚。 在一些实现中，电容器包括第一引脚和/或第二引脚。 在一些实施方式中，来自多个第一引脚的至少一个引脚横穿第二板以耦合到电容器的第一板。 在一些实现中，第二板包括翅片设计。
-
公开(公告)号：WO2014138169A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/020558
申请日：2014-03-05
Applicant: QUALCOMM INCORPORATED
Inventor： PANDEY, Shree Krishna , SUN, Changyu
IPC: G06F17/50
CPC classification number: G06F17/5081 , G06F17/5036 , G06F17/5077 , G06F2217/82
Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.
Abstract translation: 提供了一种用于无线通信的方法，装置和计算机程序产品。 该装置为由水平互连占据的一组纵向通道产生多个互连图案。 每个互连图案可以不同于其他互连图案。 每个互连图案可以限定该组水平互连和间隙通道的相对位置。 对于每个互连图案确定最高串扰，并且选择具有最小最高串扰的互连图案作为优选图案。 最高串扰可能包括远端串扰或近端串扰，并且可以针对频率范围或多个频率来计算。 可以通过将互连模型化为传输线来计算串扰。
-
公开(公告)号：WO2023278093A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/031793
申请日：2022-06-01
Applicant: QUALCOMM INCORPORATED
Inventor： XIE, Biancun , PANDEY, Shree Krishna
IPC: H01L23/50 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L25/18 , H01L25/50 , H01L27/013 , H01L28/40
Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.
-
公开(公告)号：WO2022231736A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/021679
申请日：2022-03-24
Applicant: QUALCOMM INCORPORATED
Inventor： XIE, Biancun , PANDEY, Shree Krishna , KHAN, Irfan , MIRANDA CORBALAN, Miguel , SONG, Stanley Seungchul
IPC: H01L21/48 , H01L23/14 , H01L23/498 , H01L23/50 , H01L23/538 , H01L25/065 , H01L21/768
Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.
-
公开(公告)号：WO2016122819A1
公开(公告)日：2016-08-04
申请号：PCT/US2015/068027
申请日：2015-12-30
Applicant: QUALCOMM INCORPORATED
Inventor： FU, Zhengming , DOYLE, James, Thomas , DARBANIAN, Nazanin , PANDEY, Shree Krishna , CAO, Yi
CPC classification number: G05F3/08 , G05F1/575 , H02M3/158 , H02M3/1582 , H02M2001/0045 , H02M2003/1566
Abstract: Operational mode changes in a system-on-a-chip (SoC) integrated circuit in a complex device such as a mobile phone cause spikes in current demand which can cause voltage droops that disrupt operation of the SoC. A hybrid parallel power supply capacitively couples a switching-mode power supply and a low-dropout voltage regulator in parallel to provide high efficiency and fast response times. The low-dropout voltage regulator may include a class-AB operational transconductance amplifier driving the coupling capacitor. The switching-mode power supply and the low-dropout voltage regulator can regulate their outputs to slightly difference voltage levels. This can allow the switching-mode power supply to supply most of the SoC's current demands.
Abstract translation: 诸如移动电话等复杂设备的片上系统芯片（SoC）集成电路的运行模式变化会导致电流需求上的尖峰，从而导致电压下降，从而破坏了SoC的运行。 混合并联电源并联电容耦合开关电源和低压差稳压器，以提供高效率和快速的响应时间。 低压差稳压器可以包括驱动耦合电容器的AB类运算跨导放大器。 开关电源和低压差稳压器可以将其输出调节为稍微不同的电压电平。 这可以允许开关电源供应大部分SoC的当前需求。
-
公开(公告)号：WO2009117244A1
公开(公告)日：2009-09-24
申请号：PCT/US2009/035869
申请日：2009-03-03
Applicant: QUALCOMM Incorporated , PANDEY, Shree Krishna
Inventor： PANDEY, Shree Krishna
CPC classification number: H01P3/088 , H01L2224/16227 , H01L2924/15311 , H01P5/184
Abstract: Systems having three coupled transmission lines designed in such a way that any two of which taken together can be used as a differential transmission line with a roughly equal differential mode characteristic impedance while achieving high level of common mode characteristic impedance. The high level of common mode characteristic impedance is achieved by arrangement of the three transmission lines in distinct planes along a transmission axis.
Abstract translation: 具有三个耦合传输线的系统，其设计使得其中的任何两个可以一起用作具有大致相等的差分模式特性阻抗的差分传输线，同时实现高水平的共模特性阻抗。 共模特性阻抗的高电平通过沿传输轴在不同平面中布置三条传输线来实现。
