DIGITAL IMPLEMENTATION OF ANALOG TV RECEIVER
    1.
    发明申请
    DIGITAL IMPLEMENTATION OF ANALOG TV RECEIVER 审中-公开
    模拟电视接收机的数字化实现

    公开(公告)号:WO2007008267A1

    公开(公告)日:2007-01-18

    申请号:PCT/US2006/013840

    申请日:2006-04-13

    CPC classification number: H04N9/44 H04N9/78

    Abstract: An analog TV receiver implementation on DSP allows mobile platforms to view analog TV broadcasting on LCD displays. The analog television receiver includes a demodulator for demodulating a received analog television signal, an analog to digital converter for digitizing the demodulated television signal and a digital signal processor for producing display signals from the digitized television signals. The digital signal processor being programmed to search for a horizontal synchronization signal in the television signal, track the horizontal synchronization signal and search for a vertical synchronization signal in the television signal. Next the processor separates a luminance and a pair of chrominance components of the television signal and demodulates the pair of chrominance components. Red, green and blue values are constructed from the demodulated chrominance components and the luminance components. Display signals are produced from the red, green and blue values.

    Abstract translation: DSP上的模拟电视接收机实现允许移动平台在LCD显示器上查看模拟电视广播。 模拟电视接收机包括用于解调所接收的模拟电视信号的解调器,用于数字化解调的电视信号的模数转换器和用于从数字化电视信号产生显示信号的数字信号处理器。 数字信号处理器被编程为在电视信号中搜索水平同步信号,跟踪水平同步信号并搜索电视信号中的垂直同步信号。 接下来,处理器分离电视信号的亮度和一对色度分量,并解调该对色度分量。 红色,绿色和蓝色值由解调的色度分量和亮度分量构成。 显示信号由红色,绿色和蓝色值产生。

    METHOD FOR RECOGNITION OF ACYCLIC INSTRUCTION PATTERNS
    2.
    发明申请
    METHOD FOR RECOGNITION OF ACYCLIC INSTRUCTION PATTERNS 审中-公开
    用于识别ACYCLIC指令模式的方法

    公开(公告)号:WO2006020729A2

    公开(公告)日:2006-02-23

    申请号:PCT/US2005/028463

    申请日:2005-08-11

    CPC classification number: G06F8/443

    Abstract: A method which determines by an optimizing compiler whether any variable in the given program equals to the given acyclic mathematical function f(x,y,...) applied to the given variables x, y, ... in the program. In one embodiment, the method includes expressing the bits of the value of the function f(x,y,..) as a Boolean function of the bits of the inputs x, y, ...; expressing, for every variable v and program statement s, the value taken by v when s is executed as a Boolean function V(s,v)(x, y, ...) of the bits of x, y, ...; and expressing, for every statement s, the condition under which the statement is executed as a Boolean function C(s)(x, y, ...) of the bits of the inputs x, y, .... Finally, a determination is made using a Boolean satisfiability oracle of whether, for the given variable v and program statement s, the following Boolean expression holds: C(s)(x,y,...) P> V(s,v)(x,y...)=f(x,y,...). In a second embodiment, the method includes expressing the value of f(x,y,...) as a plurality of functions f j (x,y,..) having the corresponding predicate P j (x,y,..); expressing, for every variable v and program statement s, the value taken by v when s is executed as a plurality of functions V j (s,v)(x,y,...), one for each predicate P j (x,y,..); and expressing, for every statement s, the condition under which the statement is executed as a plurality of functions C j (s)(x,y,...), one for each predicate P j (x,y,..). Finally, a determination is of whether for the given variable v and program statement s, V j (s,v)(x,y,...)=f j (x,y,..) whenever the predicate P j (x,y,..) and the condition C j (s)(x,y,...) are true.

    Abstract translation: 一种通过优化编译器确定给定程序中的任何变量是否等于给定的非循环数学函数f(x,y,...)的方法,该函数应用于程序中的给定变量x,y,...。 在一个实施例中,该方法包括将函数f(x,y,...)的值的位表示为输入x,y,...的位的布尔函数; 表示对于每个变量v和程序语句s,当s作为x,y,...的位的布尔函数V(s,v)(x,y,...)执行时,由v取得的值 ; 并且对于每个陈述s,表达作为输入x,y,...的位的布尔函数C(s,x,y,...)执行语句的条件。最后,a 对于给定的变量v和程序语句s,以下布尔表达式是否成立:C(s)(x,y,...)P> V(s,v)(x ,Y ...)= F(X,Y,...)。 在第二实施例中,该方法包括将f(x,y,...)的值表示为具有相应谓词P'的多个函数f(x,y,...) SUB>Ĵ(X,Y,...); 表示对于每个变量v和程序语句s,当s被执行为多个函数V S(s,v)(x,y,...)时,由v采取的值 对于每个谓词P< j>(x,y,...); 并且对于每个陈述s,表示执行该语句作为多个函数C(x,y,...)的条件,对于每个谓词P Ĵ(X,Y,...)。 最后,确定对于给定变量v和程序语句s,V j(s,v)(x,y,...)= f j j (x,y,...)和(x,y,...)(x,y,...)(x,y,...) 。)是真的。

    METHOD AND SYSTEM FOR PARALLELIZATION OF PIPELINED COMPUTATIONS
    3.
    发明申请
    METHOD AND SYSTEM FOR PARALLELIZATION OF PIPELINED COMPUTATIONS 审中-公开
    用于流水线计算的并行化的方法和系统

    公开(公告)号:WO2008060948A2

    公开(公告)日:2008-05-22

    申请号:PCT/US2007/084113

    申请日:2007-11-08

    CPC classification number: G06F9/5066 G06F9/3826 G06F9/3885 G06F9/5027

    Abstract: A method of parallelizing a pipeline includes stages operable on a sequence of work items. The method includes allocating an amount of work for each work item, assigning at least one stage to each work item, partitioning the at least one stage into at least one team, partitioning the at least one team into at least one gang, and assigning the at least one team and the at least one gang to at least one processor. Processors, gangs, and teams are juxtaposed near one another to minimize communication losses.

    Abstract translation: 并行化流水线的方法包括可在一系列工作项目上操作的阶段。 该方法包括为每个工作项目分配工作量,为每个工作项目分配至少一个阶段,将至少一个阶段划分成至少一个团队,将至少一个团队划分成至少一个团伙,以及将 至少一个团队和至少一个团伙到至少一个处理器。 处理器,帮派和团队彼此并置,以尽量减少通信损失。

    METHOD FOR RECOGNITION OF FULL-WORD SATURATING ADDITION AND SUBTRACTION
    4.
    发明申请
    METHOD FOR RECOGNITION OF FULL-WORD SATURATING ADDITION AND SUBTRACTION 审中-公开
    用于识别全字饱和添加和分离的方法

    公开(公告)号:WO2005098618A1

    公开(公告)日:2005-10-20

    申请号:PCT/US2004/006870

    申请日:2004-03-08

    CPC classification number: G06F8/4441

    Abstract: A method of formulating and solving equations that facilitate recognition of full word saturating addition and subtraction The method includes formulating, for each basis addition statement z = x + y or subtraction statement z = x y , data flow equations that describe properties of the program statements being analyzed; and solving the data flow equations. The properties may include: (a) the values BITS of program variables as Boolean functions of the sign bits of x , y and z ; (b) the condition COND under which program statements are executed as Boolean functions of the sign bits of x , y and z ; and (c) the condition REACH of which values of variables reach any given use of z when overflow/underflow/neither occurs.

    Abstract translation: 一种制定和求解有助于识别全字饱和加法和减法的方程的方法该方法包括为每个基础加法语句z = x + y或减法语句z = xy制定数据流方程,描述程序语句的属性 分析; 并解决数据流方程。 属性可以包括:(a)程序变量的值BITS作为x,y和z的符号位的布尔函数; (b)作为x,y和z的符号位的布尔函数执行程序语句的条件COND; 和(c)当溢出/下溢/不发生时,变量的值达到任何给定使用z的条件REACH。

    DOPPLER COMPENSATED RECEIVER
    5.
    发明申请
    DOPPLER COMPENSATED RECEIVER 审中-公开
    多普勒补偿接收器

    公开(公告)号:WO2005008274A1

    公开(公告)日:2005-01-27

    申请号:PCT/US2004/021656

    申请日:2004-07-07

    CPC classification number: G01S19/37 G01S19/29 Y10S367/904

    Abstract: A receiver includes a controller which receives A/D sampled input signals and shifts the sampled digital signal to compensate for Doppler effect in the input signal prior to demodulation. The controller compensates for a Doppler increased frequency by shifting the sampled digital signal so as to skip a sample period every n samples. This may be achieved by decreasing a cycle of m samples by one sample period every n samples. The controller compensates for a Doppler decreased frequency by shifting the sampled digital signal so as to add a sample period every n samples. This may be achieved by repeating a sample every n samples to shift the sampled digital signal. The compensation is performed in software on a multi-threaded processor.

    Abstract translation: 接收机包括控制器,其接收A / D采样输入信号并移位采样的数字信号以补偿在解调之前的输入信号中的多普勒效应。 控制器通过移位采样的数字信号来补偿多普勒增加的频率,以便每n个样本跳过采样周期。 这可以通过每n个样本减少一个采样周期的m个采样来实现。 控制器通过移位采样的数字信号来补偿多普勒降低的频率,以便每n个样本添加采样周期。 这可以通过每n个样本重复样本来实现,以移位采样的数字信号。 补偿在多线程处理器的软件中执行。

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