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公开(公告)号：WO2008124760A3
公开(公告)日：2008-11-27
申请号：PCT/US2008059740
申请日：2008-04-09
Applicant: SANDISK CORP , CERNEA RAUL-ADRIAN
Inventor： CERNEA RAUL-ADRIAN
CPC classification number: G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
Abstract: In a nonvolatile memory having an array of memory cells, wherein the memory cells are individually programmable to one of a range of threshold voltage levels, there is provided a predictive programming mode in which a predetermined function predicts what programming voltage level needs to be applied in order to program a given memory cell to a given target threshold voltage level. In this way, no verify operation needs to be performed, thereby greatly improving the performance of the programming operation. In a preferred embodiment, the predetermined function is linear and is calibrated for each memory cell under programming by one or more checkpoints. The checkpoint is an actual programming voltage that programs the memory cell in question to a verified designated threshold voltage level.
Abstract translation: 在具有存储器单元阵列的非易失性存储器中，其中存储器单元可个别地编程到阈值电压电平范围中的一个，提供了预测编程模式，其中预定函数预测编程电压电平需要施加在 为了将给定的存储器单元编程到给定的目标阈值电压电平。 这样就不需要执行验证操作，从而大大提高了编程操作的性能。 在一个优选实施例中，预定函数是线性的并且在编程时通过一个或多个检查点针对每个存储器单元进行校准。 检查点是一个实际的编程电压，用于将所讨论的存储单元编程为经验证的指定阈值电压电平。
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2.发明申请NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN REMOTE BUFFER CIRCUITS 审中-公开非易失性存储器和冗余数据在远程缓冲电路中缓存的方法
公开(公告)号：WO2007112202A3
公开(公告)日：2007-11-15
申请号：PCT/US2007063912
申请日：2007-03-13
Applicant: SANDISK CORP , CERNEA RAUL-ADRIAN
Inventor： CERNEA RAUL-ADRIAN
CPC classification number: G11C7/106 , G11C7/1039 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C16/04 , G11C29/846
Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.
Abstract translation: 存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。 在用户和冗余部分的列电路中的数据锁存允许从或被写入存储器的数据与数据总线交换。 远程冗余方案具有从任何数量的列电路可访问的中央缓冲器可用的冗余数据。 冗余数据缓冲电路可以实现总线与来自用户数据锁存器的数据的交换，除了从中央缓冲区获取数据时，缺陷位置除外。 以这种方式，仅用于用户部分的寻址用于总线交换。 此外，冗余数据的可访问性不会受到列电路相对于冗余数据锁存器的位置的限制，并且缓冲的冗余数据可以以比由列电路施加的细的粒度访问。
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3.发明申请NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开非易失性存储器和冗余数据缓存在数据锁存器中用于故障位置的方法
公开(公告)号：WO2007112201A2
公开(公告)日：2007-10-04
申请号：PCT/US2007063863
申请日：2007-03-13
Applicant: SANDISK CORP , MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
Inventor： MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
CPC classification number: G11C7/1063 , G11C7/1039 , G11C7/1051 , G11C16/04 , G11C16/10 , G11C29/846
Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
Abstract translation: 存储器在其用户部分中具有可由冗余部分中的冗余位置替换的缺陷位置。 用户和冗余部分中的数据锁存器允许从存储器读出或写入存储器的数据与数据总线交换。 有缺陷的位置锁存冗余方案假定列电路包括有缺陷列的数据锁存器仍然可用。 用于缺陷列的数据锁存器用于缓冲通常可从冗余部分的数据锁存器访问的相应冗余数据。 通过这种方式，用户数据锁存器和冗余数据都可以从用户数据锁存器中获得，并且流入或流出数据总线的数据流简化并提高了性能。
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4.发明申请
公开(公告)号：WO2009152037A3
公开(公告)日：2010-03-18
申请号：PCT/US2009046318
申请日：2009-06-04
Applicant: SANDISK CORP , CERNEA RAUL-ADRIAN
Inventor： CERNEA RAUL-ADRIAN
CPC classification number: G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/344
Abstract: A group of memory cells is programmed respectively to their target states in parallel using a multiple-pass programming method in which the programming voltages in the multiple passes are correlated. Each programming pass employs a programming voltage in the form of a staircase pulse train with a common step size, and each successive pass has the staircase pulse train offset from that of the previous pass by a predetermined offset level. The predetermined offset level is less than the common step size and may be less than or equal to the predetermined offset level of the previous pass. Thus, the same programming resolution can be achieved over multiple passes using fewer programming pulses than conventional method where each successive pass uses a programming staircase pulse train with a finer step size. The multiple pass programming serves to tighten the distribution of the programmed thresholds while reducing the overall number of programming pulses.
Abstract translation: 使用多通道编程方法将一组存储器单元分别编程到其目标状态，其中多遍中的编程电压相关。 每个编程通道采用具有公共步长的阶梯脉冲串形式的编程电压，并且每个连续通过具有与先前通过的阶梯脉冲序列偏移预定偏移电平。 预定的偏移水平小于公共步长，并且可以小于或等于先前通过的预定偏移水平。 因此，与传统方法相比，使用较少编程脉冲的多遍可以实现相同的编程分辨率，其中每个连续传递使用具有更精细步长的编程阶梯脉冲串。 多通道编程用于在编程脉冲的总数减少的同时收紧编程阈值的分布。
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5.发明申请NON-VOLATILE MEMORY AND METHOD WITH REDUNDANCY DATA BUFFERED IN DATA LATCHES FOR DEFECTIVE LOCATIONS 审中-公开非易失性存储器和冗余数据的方法在数据锁存器中缓存有缺陷的位置
公开(公告)号：WO2007112201B1
公开(公告)日：2008-01-03
申请号：PCT/US2007063863
申请日：2007-03-13
Applicant: SANDISK CORP , MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
Inventor： MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
CPC classification number: G11C7/1063 , G11C7/1039 , G11C7/1051 , G11C16/04 , G11C16/10 , G11C29/846
Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
Abstract translation: 存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。 用户和冗余部分中的数据锁存器允许从或被写入存储器的数据与数据总线交换。 缺陷位置锁存冗余方案假定包括有缺陷列的数据锁存器的列电路仍然可用。 用于缺陷列的数据锁存器用于缓冲通常可从冗余部分中的数据锁存器访问的相应冗余数据。 以这种方式，用户和冗余数据可从用户数据锁存器获得，并且流数据进出数据总线被简化和性能提高。
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公开(公告)号：WO2004029984A3
公开(公告)日：2004-12-23
申请号：PCT/US0329603
申请日：2003-09-23
Applicant: SANDISK CORP
Inventor： CERNEA RAUL-ADRIAN , LI YAN
CPC classification number: G11C7/062 , G11C7/067 , G11C11/5642 , G11C16/26
Abstract: Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the control gate voltage of a memory cell is erroneously biased by a voltage drop across the resistance. This error is minimized when the current flowing though the ground loop is reduced. A method for reducing source line bias is accomplished by read/write circuits with features and techniques for multi-pass sensing. When a page of memory cells are being sensed in parallel, each pass helps to identify and shut down the memory cells with conduction current higher than a given demarcation current value. In particular, the identified memory cells are shut down after all sensing in the current pass have been completed. In this way the shutting down operation does not disturb the sensing operation. Sensing in subsequent passes will be less affected by source line bias since the total amount of current flow is significantly reduced by eliminating contributions from the higher current cells. In another aspect of sensing improvement, a reference sense amplifier is employed to control multiple sense amplifiers to reduce their dependence on power supply and environmental variations.
Abstract translation: 源极偏置是由读/写电路的接地回路中的非零电阻引起的误差。 在感测期间，存储器单元的控制栅极电压被跨过电阻的电压降错误地偏置。 当通过接地回路的电流减小时，该误差被最小化。 用于减少源极偏置的方法是通过具有用于多通感测的特征和技术的读/写电路实现的。 当并行地检测到一页存储单元时，每次通过有助于识别和关闭具有高于给定分界电流值的传导电流的存储单元。 特别地，在当前通路中的所有感测完成之后，所识别的存储器单元关闭。 以这种方式，关闭操作不会影响感测操作。 在后续通过中的感测将受到源极偏置的影响较小，因为通过消除较高电流单元的贡献，电流流动的总量显着减少。 在感测改进的另一方面，采用参考读出放大器来控制多个读出放大器以减少它们对电源和环境变化的依赖。
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公开(公告)号：WO2008083136A3
公开(公告)日：2008-12-11
申请号：PCT/US2007088786
申请日：2007-12-24
Applicant: SANDISK CORP , MOKHLESI NIMA , CERNEA RAUL-ADRIAN
Inventor： MOKHLESI NIMA , CERNEA RAUL-ADRIAN
IPC: G11C16/26
CPC classification number: G11C11/5642 , G11C11/5628 , G11C16/0483 , G11C16/26
Abstract: When reading data from a non-volatile storage element that is part of a group of connected non-volatile storage elements, resistance information is measured for the group. One or more read parameters are set based on the measured resistance information. The read process is then performed using the one or more parameters.
Abstract translation: 当从作为一组连接的非易失性存储元件的一部分的非易失性存储元件读取数据时，测量该组的电阻信息。 基于所测量的电阻信息设置一个或多个读取参数。 然后使用一个或多个参数执行读取过程。
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8.发明申请
公开(公告)号：WO2007112201A9
公开(公告)日：2008-11-06
申请号：PCT/US2007063863
申请日：2007-03-13
Applicant: SANDISK CORP , MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
Inventor： MOOGAT FAROOKH , CERNEA RAUL-ADRIAN , TSAO SHOU-CHANG , TSENG TAI-YUAN
CPC classification number: G11C7/1063 , G11C7/1039 , G11C7/1051 , G11C16/04 , G11C16/10 , G11C29/846
Abstract: A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in the user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A defective location latching redundancy scheme assumes the column circuits including data latches for defective columns to be still useable. The data latches for the defective columns are used to buffer corresponding redundant data that are normally accessible from their data latches in the redundant portion. In this way both the user and redundant data are available from the user data latches, and streaming data into or out of the data bus is simplified and performance improved.
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9.发明申请REFERENCE SENSE AMPLIFIER AND METHOD FOR COMPENSATED SENSING IN NON-VOLATILE MEMORY 审中-公开参考信号放大器和非易失性存储器中的补偿感测方法
公开(公告)号：WO2007076414A3
公开(公告)日：2007-09-27
申请号：PCT/US2006062429
申请日：2006-12-20
Applicant: SANDISK CORP , CHAN SIU LUNG , CERNEA RAUL-ADRIAN
Inventor： CHAN SIU LUNG , CERNEA RAUL-ADRIAN
CPC classification number: G11C11/5642 , G11C7/06 , G11C7/14 , G11C16/26 , G11C16/32 , G11C2207/063
Abstract: One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
Abstract translation: 用于感测非易失性存储器的传导电流的一个或多个感测放大器由具有相似特性和操作条件的参考读出放大器定时的信号控制。 在一个方面，感测周期由感测参考电流的参考读出放大器何时检测到预期状态来确定。 在另一方面，放大输出的积分周期由参考读出放大器何时输出预期状态来确定。 当这些确定的定时用于控制一个或多个感测放大器时，跟踪环境和系统变化。
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公开(公告)号：WO2005017902A9
公开(公告)日：2005-05-19
申请号：PCT/US2004024064
申请日：2004-07-27
Applicant: SANDISK CORP , CERNEA RAUL-ADRIAN
Inventor： CERNEA RAUL-ADRIAN
Abstract: A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.
Abstract translation: 第一电荷泵包括一组电压加法器级。 第一电压加法器级接收输入电压VCC，并且响应于时钟信号提供在2 * VCC和VCC之间交替的第一电压信号。 第N电压加法器级从前级接收输入电压VCC和第一电压信号，并提供在N * VCC和VCC之间交替的第二电压信号。 包含在每个加法器级中的电容器需要维持VCC的最大电压。 在替代实施例中，第一电荷泵可以与一个或多个倍压器级组合以产生更高的输出电压。
