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1.发明申请PROGRAM AND READ OPERATIONS FOR 3D NON-VOLATILE MEMORY BASED ON MEMORY HOLE DIAMETER 审中-公开基于记忆孔直径的3D非易失性存储器的程序和读取操作公开(公告)号：WO2014197522A1
公开(公告)日：2014-12-11
申请号：PCT/US2014/040774
申请日：2014-06-04
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： DONG, Yingda , OU, Wendy , MUI, Man L , HIGASHITANI, Masaaki
CPC classification number: G11C16/107 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/1157 , H01L27/11582
Abstract: Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state.
Abstract translation: 提供了通过补偿存储器孔直径的变化来编程和读取3D堆叠的非易失性存储器件中的存储器单元的技术。 存储孔直径在堆叠底部较小，导致更严重的读取干扰。 为了补偿，在较低字线层处的存储器单元的编程被修改。 在一种方法中，编程期间一个或多个数据状态的阈值电压（Vth）分布变窄，从而可以在随后的感测操作中使用较低的读通过电压。 在读通道电压和最高数据状态的上尾之间保持足够的间隔。 Vth分布也可以降档。 在另一种方法中，读通道电压不降低，但是最低编程状态被升高以提供与擦除状态的上尾的间隔。
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2.发明申请ADJUSTING CONTROL GATE OVERDRIVE OF DRAIN SELECT GATE TRANSISTORS DURING PROGRAMMING OF A 3D NAND NON-VOLATILE MEMORY 审中-公开在三维非易失性存储器的编程过程中调节漏极选择栅极晶体管的控制栅极叠加
公开(公告)号：WO2014165460A1
公开(公告)日：2014-10-09
申请号：PCT/US2014/032438
申请日：2014-04-01
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： DONG, Yingda , HIGASHITANI, Masaaki
IPC: G11C11/56 , G11C16/04 , G11C16/10 , G11C16/34 , H01L27/115
CPC classification number: G11C16/12 , G11C11/5628 , G11C16/0475 , G11C16/0483 , G11C16/10 , G11C16/3427 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/4983
Abstract: In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided.
Abstract translation: 在3D堆叠的非易失性存储器件中，多个更小的漏极端选择栅极（SGD）晶体管代替一个较大的SGD晶体管。 SGD晶体管具有不同的控制栅极过驱动电压，使得在编程操作期间，在禁止的NAND串中产生不连续的沟道电位。 最靠近位线的SGD晶体管具有较低的控制栅极过驱动电压，使得其下的沟道电位较低，并且下一个SGD晶体管具有较高的控制栅极过驱动电压，使得其下的沟道电位较高。 可以通过编程不同的阈值电压或通过为SGD晶体管提供不同的控制栅极电压来提供不同的控制栅极过驱动电压。 可以避免由于漏极引起的屏障降低导致的Vsgd窗口的不期望的减少。
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3.发明申请NON-VOLATILE STORAGE NAND STRING SELECT GATE VOLTAGE LOWERED DURING PROGRAMMING 审中-公开非易失性存储NAND STRING在编程期间选择门电压降低
公开(公告)号：WO2014088803A1
公开(公告)日：2014-06-12
申请号：PCT/US2013/070841
申请日：2013-11-19
Applicant: SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
Inventor： DUTTA, Deepanshu , SATO, Shinji , HIGASHITANI, Masaaki , YANO, Fumiko , LAI, Chun-Hung
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/24
Abstract: Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.
Abstract translation: 本文公开的技术可以通过防止未选择的NAND串的选择晶体管无意地导通来阻止程序干扰。 NAND串的选择晶体管的Vgs可以从一个编程脉冲多次降低到下一个编程脉冲。 选择晶体管可以是漏极侧选择晶体管或源极侧选择晶体管。 随着编程进行，逐渐降低未选择的NAND串的选择晶体管的Vgs可以防止选择晶体管无意地导通。 因此，防止或减少程序干扰。 可以通过对与选择晶体管相关联的选择线施加较低的电压来降低Vgs。 当编程进行时，可以通过对与未选择的NAND串相关联的位线施加更高的电压来降低Vgs。 当编程进行时，Vgs可以通过对公共源极线施加更高的电压来降低。
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4.发明申请
公开(公告)号：WO2013176858A1
公开(公告)日：2013-11-28
申请号：PCT/US2013/039209
申请日：2013-05-02
Applicant: SANDISK TECHNOLOGIES, INC. , DUTTA, Deepanshu , DUNGA, Mohan , HIGASHITANI, Masaaki
Inventor： DUTTA, Deepanshu , DUNGA, Mohan , HIGASHITANI, Masaaki
CPC classification number: G11C16/14 , G11C7/1006 , G11C11/5635 , G11C16/0483 , G11C16/16
Abstract: A technique for erasing non-volatile memory such as a NAND string which includes non-user data or dummy storage elements. The voltages of the non-user data storage elements are capacitively coupled higher by controlled increases in an erase voltage which is applied to a substrate. The voltages are floated by rendering a pass gate transistor in a non-conductive state, where the pass gate transistor is between a voltage driver and a non-user data storage element. Voltages of select gate transistors can also be capacitively coupled higher. The substrate voltage can be increased in steps and/or as a continuous ramp. In one approach, outer dummy storage elements are floated while inner dummy storage elements are driven. In another approach, both outer and inner dummy storage elements are floated. Write-erase endurance of the storage elements is increased due to reduced charge trapping in the substrate.
Abstract translation: 一种用于擦除诸如包括非用户数据或虚拟存储元件的NAND串的非易失性存储器的技术。 非用户数据存储元件的电压通过施加到衬底的擦除电压的受控增加而被电容性耦合。 通过使通路栅极晶体管处于非导通状态来浮置电压，其中通过栅极晶体管位于电压驱动器和非用户数据存储元件之间。 选择栅极晶体管的电压也可以电容耦合得更高。 衬底电压可以逐步增加和/或作为连续斜坡增加。 在一种方法中，外部虚拟存储元件浮动，同时内部虚拟存储元件被驱动。 在另一种方法中，外部和内部虚拟存储元件都浮起来。 由于基板中的电荷捕获减少，存储元件的写擦除耐久性增加。
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5.发明申请FABRICATING 3D NON-VOLATILE STORAGE WITH ADDITIONAL WORD LINE SELECT GATES 审中-公开使用附加字线选择门框制作3D非易失性存储
公开(公告)号：WO2013155329A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/036213
申请日：2013-04-11
Applicant: SANDISK TECHNOLOGIES, INC. , RABKIN, Peter , HIGASHITANI, Masaaki
Inventor： RABKIN, Peter , HIGASHITANI, Masaaki
IPC: H01L29/66 , H01L29/786 , H01L27/115 , H01L21/265 , G11C16/08
CPC classification number: H01L29/66757 , G11C16/0483 , G11C16/06 , G11C16/08 , H01L21/02532 , H01L21/02595 , H01L21/04 , H01L21/26513 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/66477 , H01L29/66742 , H01L29/6675 , H01L29/66787 , H01L29/785 , H01L29/78642 , H01L29/78696 , H01L29/7926
Abstract: Disclosed herein are techniques for fabricating a 3D stacked memory device having word line (WL) select gates (229). The bodies (231) of the WL select gates may be formed from the same material (e.g., highly doped polysilicon) that the word lines are formed of. Desired doping profiles in a body of a WL select gate may be achieved by various techniques such as counter-doping. The WL select gates may include TFTs that are formed by etching holes in the layer in which word lines are formed. Gate electrodes (404) and gate dielectrics (402) may be formed in the holes. Bodies may be formed in the polysilicon outside of the holes.
Abstract translation: 这里公开了用于制造具有字线（WL）选择门（229）的3D堆叠存储器件的技术。 WL选择栅极的主体（231）可以由字线形成的相同材料（例如，高掺杂多晶硅）形成。 可以通过各种技术（例如反掺杂）来实现在WL选择栅极的体内期望的掺杂分布。 WL选择栅极可以包括通过在其中形成字线的层中蚀刻孔而形成的TFT。 可以在孔中形成栅极（404）和栅极电介质（402）。 体可以形成在孔外的多晶硅中。
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公开(公告)号：WO2013155325A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/036208
申请日：2013-04-11
Applicant: SANDISK TECHNOLOGIES, INC. , RABKIN, Peter , HIGASHITANI, Masaaki
Inventor： RABKIN, Peter , HIGASHITANI, Masaaki
IPC: H01L29/66 , H01L29/786 , H01L27/115 , H01L21/265 , G11C16/08
CPC classification number: H01L29/66757 , G11C16/0483 , G11C16/06 , G11C16/08 , H01L21/02532 , H01L21/02595 , H01L21/04 , H01L21/26513 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L27/1222 , H01L27/1259 , H01L29/42384 , H01L29/66477 , H01L29/66742 , H01L29/6675 , H01L29/66787 , H01L29/785 , H01L29/78642 , H01L29/78696 , H01L29/7926
Abstract: Disclosed herein are 3D stacked memory devices having WL select gates (229). The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area (301) of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors (231, 402, 404). 3D decoding may be provided in a 3D stacked memory device using the WL select gates.
Abstract translation: 这里公开了具有WL选择门的3D堆叠存储器件（229）。 3D堆叠存储器件可以具有NAND串。 WL选择栅极可以位于与字线板的字线连接区域（301）相邻的位置。 字线板可以由字线驱动器驱动，并且可以具有许多字线。 WL选择门可以选择单个字线或字线组。 因此，可以选择整个块的较小单元。 这可能会降低电容负载。 WL选择栅极可以包括薄膜晶体管（231,402,404）。 可以使用WL选择门在3D堆叠存储器件中提供3D解码。
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公开(公告)号：WO2011149823A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/037526
申请日：2011-05-23
Applicant: SANDISK TECHNOLOGIES, INC. , MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
Inventor： MOKHLESI, Nima , CHIN, Henry , HIGASHITANI, Masaaki
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/10
Abstract: A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected tol5 a group of connected non-volatile storage elements. The set of word lines includes a selected word line(WLn), unselected word lines (WLn+1/WLn- 1) that are adjacent to the selected word line and other unselected word lines (WLunse1). After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage (Vpgm) and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels (Vint1, Vint2, Vint3 ) concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
Abstract translation: 用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。 编程过程包括提高连接到一组连接的非易失性存储元件的一组字线的电压。 该字线组包括与所选择的字线和其他未被选择的字线（WLunse1）相邻的所选字线（WLn），未选字线（WLn + 1 / WLn-1）。 在对所述一组字线提升电压之后，所述处理包括将所选择的字线升高到编程电压（Vpgm），并将与所选字线相邻的未选字线提升到一个或多个电压电平（Vint1，Vint2， Vint3）同时将选定的字线提升到编程电压。 程序电压使至少一个非易失性存储元件经历编程。
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公开(公告)号：WO2016085565A1
公开(公告)日：2016-06-02
申请号：PCT/US2015/052075
申请日：2015-09-24
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： RABKIN, Peter , ALSMEIER, Johann , HIGASHITANI, Masaaki
IPC: H01L27/115 , H01L21/28 , H01L21/02 , H01L29/423 , H01L29/66 , H01L29/786 , H01L29/792
CPC classification number: H01L29/24 , H01L21/02565 , H01L21/02631 , H01L21/28282 , H01L27/1157 , H01L27/11578 , H01L27/11582 , H01L29/4234 , H01L29/66969 , H01L29/7869 , H01L29/7926
Abstract: Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The NAND string comprises a vertically-oriented cylindrically shaped channel (699), the vertically-oriented cylindrically shaped channel comprising an oxide semiconductor having a crystalline structure, the crystalline structure having an axis (a, b, or c) that is aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically- oriented channel. The crystalline structure may, for example, have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc.
Abstract translation: 这里公开了具有氧化物半导体垂直NAND通道的3D NAND存储器件及其形成方法。 NAND串包括垂直取向的圆柱形通道（699），垂直取向的圆柱形通道包括具有晶体结构的氧化物半导体，该晶体结构具有与（α，b或c） 相对于垂直取向的通道的圆柱形形状，基本上遍及垂直定向的通道。 晶体结构可以例如具有平行于垂直通道对准的第一轴线，垂直于圆柱形通道的表面对准的第二轴线等
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9.发明申请VREAD BIAS ALLOCATION ON WORD LINES FOR READ DISTURB REDUCTION IN 3D NON-VOLATILE MEMORY 审中-公开用于在3D非易失性存储器中读取干扰减少的字线上的VREAD偏差分配
公开(公告)号：WO2015038558A1
公开(公告)日：2015-03-19
申请号：PCT/US2014/054865
申请日：2014-09-09
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： DONG, Yingda , ZHANG, Chenfeng , OU, Wendy , YU, Seung , HIGASHITANI, Masaaki
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3427
Abstract: Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.
Abstract translation: 提供技术以通过使用基于存储器孔直径的变化进行调整的读通过电压来以减少读取干扰的方式感测3D堆叠的非易失性存储器件中的存储器单元。 存储器单元是在存储器孔中延伸的NAND串。 与存储器孔的较宽部分相邻的存储单元使用较大的读取通过电压，并且与存储器孔的较窄部分相邻的存储器单元使用较小的读取通过电压。 这种方法减少了最坏情况的读取干扰。 此外，NAND串通道中的整体电阻可以基本上不变，使得在感测期间使用的参考电流可以不变。 可以基于指示编程速度和存储器孔直径的编程电压调整值来设置读取通过电压。
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10.发明申请3D NON-VOLATILE MEMORY WITH CONTROL GATE LENGTH BASED ON MEMORY HOLE DIAMETER 审中-公开基于记忆孔直径的具有控制门长度的3D非易失性存储器
公开(公告)号：WO2014197523A1
公开(公告)日：2014-12-11
申请号：PCT/US2014/040775
申请日：2014-06-04
Applicant: SANDISK TECHNOLOGIES INC.
Inventor： DONG, Yingda , OU, Wendy , MUI, Man L , HIGASHITANI, Masaaki
IPC: H01L27/115 , G11C16/04 , G11C16/34
CPC classification number: G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/107 , G11C16/3418 , G11C16/3445 , G11C16/3472 , H01L27/11582 , H01L29/7926
Abstract: A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.
Abstract translation: 提供了用于补偿存储器孔直径的变化的3D堆叠的非易失性存储器件的结构和制造工艺。 存储孔直径在堆叠底部较小，导致更严重的读取干扰。 为了补偿，字线层在堆叠的底部较厚，并且可以从堆叠的底部到顶部逐渐增加。 结果，存储器单元的控制栅极的长度在堆叠的底部更大。 控制栅极和电荷捕获层之间的电容与控制栅极的长度成比例地增加。 在编程期间，对于这些存储单元实现了较窄的阈值电压（Vth）分布。 可以将Vth分布放置得更靠近在一起并降档以允许在随后的感测操作中降低读通过电压，从而减少读取干扰。
