公开(公告)号：WO2018004753A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/019591

申请日：2017-02-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： PANG, Liang ,  DONG, Yingda ,  YU, Xuehong ,  REN, Jingjian

IPC: G11C16/34 ,  G11C16/26

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3459

Abstract: Techniques are disclosed for accurately sensing memory cells without having to wait for a voltage that creeps up on word line after a sensing operation to die down. The word line creep up could cause electrons to trap in shallow interface traps of a memory cell, hence impacting its threshold voltage. In one aspect, trapped electrons are removed (e.g., de-trapped) from shallow interface traps of a memory cell using a weak erase operation. Therefore, problems associated with word line voltage creep up are reduced or prevented. Thus, the memory cell can be sensed without waiting, while still providing an accurate result. The weak erase could be part of a sensing operation, but that is not required. For example, the weak erase could be incorporated into the beginning part of a read operation, which provides for a very efficient solution.

Abstract translation: 公开了用于精确地感测存储器单元而不必等待在感测操作停止之后在字线上爬升的电压的技术。 字线蠕变可能导致电子陷入存储器单元的浅界面陷阱中，从而影响其阈值电压。 在一个方面中，使用弱擦除操作从存储器单元的浅界面陷阱移除（例如，解俘获）俘获的电子。 因此，减少或防止了与字线电压蠕变相关的问题。 因此，可以在不等待的情况下感测存储器单元，同时仍然提供准确的结果。 弱擦除可能是感测操作的一部分，但这不是必需的。 例如，弱擦除可以包含在读操作的开始部分，这提供了非常有效的解决方案。

公开(公告)号：WO2017184248A1

公开(公告)日：2017-10-26

申请号：PCT/US2017/018545

申请日：2017-02-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： PANG, Liang ,  DONG, Yingda ,  YUAN, Jiahui ,  REN, Jingjian

IPC: G11C16/34 ,  G11C7/04 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/3427 ,  G11C16/3486

Abstract: Techniques are provided for avoiding over-programming can occur on memory cells connected to a data word line at a source-side of a block of word lines. A gradient in the channel potential is created during a program voltage between the data word line and an adjacent dummy word line. This gradient generates electron-hole pairs which can contribute to over programming, where the over programming is worse at higher temperatures. In one aspect, pass voltages of unselected word lines are set to be relatively lower when the temperature is relatively higher, and when the selected word line is among a set of one or more source-side word lines. On the other hand, the pass voltages are set to be relatively higher when the temperature is relatively higher, and when the selected word line is not among the one or more source-side word lines.

Abstract translation: 提供了用于避免在连接到字线块的源侧的数据字线的存储单元上发生过度编程的技术。 在数据字线和相邻虚拟字线之间的编程电压期间，产生沟道电位的梯度。 这种梯度会产生电子空穴对，这可能导致编程过度，在较高的温度下编程过度会变得更糟。 在一个方面，当温度相对较高时，以及当所选字线位于一组一个或多个源侧字线中时，未选字线的通过电压被设置为相对较低。 另一方面，当温度相对较高并且所选字线不在一个或多个源侧字线中时，通过电压被设置为相对较高。

公开(公告)号：WO2017112009A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/051365

申请日：2016-09-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： PANG, Liang ,  YUAN, Jiahui ,  DONG, Yingda ,  REN, Jingjian

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3459

Abstract: Techniques are provided for programming a three-dimensional memory device while minimizing over-programming and program disturb. When a selected word line is at the source-side of a set of word lines, a channel gradient is created in the channel adjacent to the selected word line when a program voltage is applied. The gradient generates hot carriers which can cause over-programming of memory cells connected to the selected word line. To reduce the amount of hot carriers, a ramp rate and/or duration of a first step up of the program voltage is reduced. When the selected word line is not at the source-side of the set of word lines, a baseline ramp rate and/or duration can be used. A ramp rate and/or duration of the voltage applied to unselected word lines can be reduced as well but by a lesser amount.

Abstract translation: 提供了用于编程三维存储器装置的技术，同时最小化过度编程和编程干扰。 当所选字线位于一组字线的源侧时，当施加编程电压时，在与所选字线相邻的通道中创建通道梯度。 该梯度生成热载流子，这会导致连接到所选字线的存储单元的过度编程。 为了减少热载流子的数量，降低编程电压第一次升压的斜率和/或持续时间。 当所选字线不在该组字线的源侧时，可以使用基线斜率和/或持续时间。 施加到未选字线的电压的斜坡速率和/或持续时间也可以减少，但数量较少。