公开(公告)号：WO2016022256A1

公开(公告)日：2016-02-11

申请号：PCT/US2015/040189

申请日：2015-07-13

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： YANG, Jeng-wei ,  WU, Man-tang ,  CHEN, Chun-ming ,  SU, Chien-sheng ,  DO, Nhan

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

Abstract: A non- volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate there between. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

Abstract translation: 非易失性存储单元包括在第二导电类型的衬底中的第一导电类型，第一和第二间隔开的区域的半导体衬底，其中衬底中的沟道区域。 浮动栅极具有垂直设置在沟道区域的第一部分上的第一部分和垂直设置在第一区域上的第二部分。 浮动门包括倾斜的上表面，其以一个或多个尖锐边缘终止。 擦除栅极垂直设置在浮动栅极上，其中一个或多个尖锐边缘面向擦除栅极。 控制门具有横向邻近浮动栅极设置的第一部分，并且垂直地设置在第一区域上。 选择栅极具有垂直设置在沟道区域的第二部分上并且横向邻近浮置栅极的第一部分。

公开(公告)号：WO2016111796A1

公开(公告)日：2016-07-14

申请号：PCT/US2015/064534

申请日：2015-12-08

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： CHEN, Chun-ming ,  WU, Man-tang ,  YANG, Jeng-wei ,  SU, Chien-sheng

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A non- volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

Abstract translation: 非挥发性存储单元包括第一导电类型的衬底，具有第二导电类型的第一区域，与第一区域间隔开的第二导电类型的第二区域，在其间形成沟道区域。 浮置栅极设置在与第一区域相邻的沟道区域的第一部分之上并与其绝缘。 选择栅极设置在与第二区域相邻的沟道区域的第二部分上，选择栅极由金属材料形成并且通​​过二氧化硅层和高层与沟道区域的第二部分绝缘 K绝缘材料。 控制栅极设置在浮动栅极上并与浮动栅极绝缘。 擦除栅极设置在第一区域之上并与第一区域绝缘，并且布置成横向邻近并与浮动栅极绝缘。

公开(公告)号：WO2016043857A1

公开(公告)日：2016-03-24

申请号：PCT/US2015/043429

申请日：2015-08-03

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-sheng ,  TRAN, Hieu, Van ,  TADAYONI, Mandana ,  DO, Nhan ,  YANG, Jeng-wei

IPC: H01L21/28 ,  H01L29/66 ,  H01L27/115 ,  H01L27/12

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

公开(公告)号：WO2015002923A1

公开(公告)日：2015-01-08

申请号：PCT/US2014/045003

申请日：2014-07-01

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-sheng ,  YANG, Jeng-wei ,  CHEN, Yueh-hsin

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L27/115

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/823425 ,  H01L29/1608 ,  H01L29/42328 ,  H01L29/66825

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

Abstract translation: 一种具有一对导电浮动栅极的存储器件，所述导电浮动栅极具有彼此面对的内侧壁，并且设置在第一导电类型的衬底上并与其绝缘。 一对间隔开的导电控制栅极，每个导电控制栅极设置在浮动栅极中的一个上并与之隔绝，并且每个包括彼此面对的内侧壁。 一对绝缘材料的第一间隔物，沿着控制栅极内侧壁和浮动栅极延伸。 浮动门内侧壁与第一间隔件的侧表面对准。 绝缘材料的一对第二间隔物各自沿着第一间隔件中的一个并且沿着浮动栅极内侧壁中的一个延伸。 形成在衬底中的沟槽，其具有与第二间隔物的侧表面对齐的侧壁。 设置在沟槽中的硅碳。 材料注入到硅碳中，形成具有第二导电类型的第一区域。

公开(公告)号：WO2014143408A1

公开(公告)日：2014-09-18

申请号：PCT/US2014/011934

申请日：2014-01-16

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： SU, Chien-sheng ,  YANG, Jeng-wei ,  TADAYONI, Mandana ,  CHEN, Yueh-hsin

IPC: H01L21/336

CPC classification number: H01L29/66477 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method of forming an MOS transistor by forming a poly gate over and insulated from a substrate, forming a layer of protective insulation material on the poly gate, and then performing a first implant of dopant material into portions of the substrate adjacent the poly gate, wherein the layer of protective insulation material and the poly gate block most or all of the first implant from reaching a portion of the substrate underneath the poly gate. One or more spacers are then formed adjacent the poly gate, followed by a second implant of dopant material into portions of the substrate adjacent to the one or more spacers.

Abstract translation: 一种形成MOS晶体管的方法，该方法是在多晶硅栅极上形成保护绝缘材料层，然后在邻近多晶硅栅极的基板的第一部分中进行第一次掺杂， 其中所述保护绝缘材料层和所述多晶硅栅极阻挡所述第一注入的大部分或全部到达所述多晶硅栅极下方的所述衬底的一部分。 然后在多晶硅栅极附近形成一个或多个间隔物，随后将掺杂剂材料第二次注入到与该一个或多个间隔物相邻的衬底的部分中。