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    HIGH CAPACITY MEMORY MODULE INCLUDING WAFER-SECTION MEMORY CIRCUIT
    1.
    发明申请
    HIGH CAPACITY MEMORY MODULE INCLUDING WAFER-SECTION MEMORY CIRCUIT 审中-公开

    公开(公告)号：WO2021173209A1

    公开(公告)日：2021-09-02

    申请号：PCT/US2020/065374

    申请日：2020-12-16

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： NORMAN, Robert ,  CHERNICOFF, Richard S. ,  HARARI, Eli

    IPC: H01L25/065 ,  G06F12/0802 ,  G06F13/28 ,  G11C5/02 ,  G11C11/401 ,  H01L25/00

    Abstract: A memory device includes a first semiconductor wafer portion including two or more adjacent quasi-volatile memory circuits formed on a common semiconductor substrate where each quasi-volatile memory circuit being isolated from an adjacent quasi-volatile memory circuit by scribe lines; and a second semiconductor wafer portion including at least one memory controller circuit formed on a semiconductor substrate. The memory controller circuit includes logic circuits and interface circuits. The memory controller circuit is interconnected to the two or more adjacent quasi-volatile memory circuits of the first semiconductor wafer portion through interconnect structures and the memory controller circuit operates the two or more quasi-volatile memory circuits as one or more quasi-volatile memories.

    PROCESSES FOR FORMING 3-DIMENSIONAL HORIZONTAL NOR MEMORY ARRAYS
    6.
    发明申请
    PROCESSES FOR FORMING 3-DIMENSIONAL HORIZONTAL NOR MEMORY ARRAYS 审中-公开

    公开(公告)号：WO2020236611A1

    公开(公告)日：2020-11-26

    申请号：PCT/US2020/033180

    申请日：2020-05-15

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： HARARI, Eli ,  CHIEN, Wu-Yi Henry

    IPC: G11C11/40 ,  G11C16/04 ,  H01L27/11582

    Abstract: A process forms thin-film storage transistors (e.g., HNOR devices) with improved channel regions by conformally depositing a thin channel layer in a cavity bordering a source region and a drain region, such that a portion of the channel material abuts by junction contact the source region and another portion of the channel layer abut by junction contact the drain region. The cavity is also bordered by a storage layer. In one form of the process, the channel region is formed before the storage layer is formed. In another form of the storage layer is formed before the channel region is formed.

    3-DIMENSIONAL NOR MEMORY ARRAY WITH VERY FINE PITCH: DEVICE AND METHOD
    7.
    发明申请
    3-DIMENSIONAL NOR MEMORY ARRAY WITH VERY FINE PITCH: DEVICE AND METHOD 审中-公开

    公开(公告)号：WO2019133534A1

    公开(公告)日：2019-07-04

    申请号：PCT/US2018/067338

    申请日：2018-12-21

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： HARARI, Eli ,  HERNER, Scott Brad ,  CHIEN, Wu-Yi

    IPC: G11C16/04 ,  H01L29/06

    Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

    THREE-DIMENSIONAL NOR MEMORY STRING ARRAYS OF THIN-FILM FERROELECTRIC TRANSISTORS
    8.
    发明申请
    THREE-DIMENSIONAL NOR MEMORY STRING ARRAYS OF THIN-FILM FERROELECTRIC TRANSISTORS 审中-公开

    公开(公告)号：WO2023033987A1

    公开(公告)日：2023-03-09

    申请号：PCT/US2022/039473

    申请日：2022-08-04

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： PETTI, Christopher J. ,  HARARI, Eli

    IPC: G11C11/22 ,  H01L27/11597 ,  H01L27/11582 ,  H01L27/11585

    Abstract: A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent a semiconductor channel. In some embodiments, the semiconductor channel is formed by an oxide semiconductor material and the ferroelectric storage transistors are junctionless transistors with no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a first conductive layer as a common source line and a second conductive layer as a common bit line, the first and second conductive layers being in electrical contact with the semiconductor channel. The ferroelectric storage transistors in a multiplicity of NOR memory strings are arranged to form semi-autonomous three-dimensional memory arrays (tiles) with each tile individually addressed and controlled by circuitry in the semiconductor substrate underneath each tile in cooperation with a memory controller.

    CHANNEL CONTROLLER FOR SHARED MEMORY ACCESS
    9.
    发明申请
    CHANNEL CONTROLLER FOR SHARED MEMORY ACCESS 审中-公开

    公开(公告)号：WO2021173572A1

    公开(公告)日：2021-09-02

    申请号：PCT/US2021/019270

    申请日：2021-02-23

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： NORMAN, Robert D. ,  CHERNICOFF, Richard S. ,  HARARI, Eli

    IPC: G06F15/76 ,  G06F9/00

    Abstract: A shared memory provides multi-channel access from multiple computing or host devices. A priority circuit prioritizes the multiple memory requests that are submitted as bids from the multiple host channels, such that those memory access requests that do not give rise to a conflict may proceed in parallel. The shared memory may be multi-ported and a routing circuit routes the prioritized memory access request to the appropriate memory ports where the allowed memory access requests may be carried out.

    PROCESS FOR PREPARING A CHANNEL REGION OF A THIN-FILM TRANSISTOR
    10.
    发明申请
    PROCESS FOR PREPARING A CHANNEL REGION OF A THIN-FILM TRANSISTOR 审中-公开

    公开(公告)号：WO2021127218A1

    公开(公告)日：2021-06-24

    申请号：PCT/US2020/065670

    申请日：2020-12-17

    Applicant: SUNRISE MEMORY CORPORATION

    Inventor： PURAYATH, Vinod ,  ZHOU, Jie ,  CHIEN, Wu-Yi Henry ,  HARARI, Eli

    IPC: H01L21/76 ,  H01L27/115 ,  H01L21/3065 ,  H01L27/1052 ,  H01L29/6675 ,  H01L29/78642 ,  H01L29/78663 ,  H01L29/78672

    Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layer wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation laye (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material.

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