公开(公告)号：WO9008362A3

公开(公告)日：1990-09-07

申请号：PCT/US9000266

申请日：1990-01-12

Applicant: VLSI TECHNOLOGY INC

Inventor： ASATO CREIGHTON SATOSHI ,  DHOLAKIA SURESH KISHORBHAI ,  DITZEN CHRISTOPH

IPC: G06F7/53 ,  G06F7/00 ,  G06F7/506 ,  G06F7/527 ,  G06F9/38 ,  G06F17/50 ,  G06F15/60

CPC classification number: G06F17/5045 ,  G06F7/00 ,  G06F9/3875

Abstract: According to a technique for determining delays through multi-stage datapath elements, estimates of the delays through each stage of the datapath element are computed in accordance with an equation such as: Ds=DbNb+C; where Ds is the estimated stage delay, Db is a delay associated with communication between bits in the stage, Nb is the number of bits in the datapath element, and C is a constant. The estimated stage delays are used to determine positions of pipelining stages in the datapath element.