公开(公告)号：WO2017189088A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/020076

申请日：2017-03-01

Applicant: WESTERN DIGITAL TECHNOLOGIES INC.

Inventor： BEDAU, Daniel

IPC: G11C13/00

CPC classification number: H01L27/249 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C2213/53 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a multi-layer resistive random access memory (ReRAM) array is provided. Active layers of the array each comprise a plurality of ReRAM elements that each include a gate portion having a gate terminal and a memory cell portion with a source terminal and drain terminal. Insulating layers of the array alternate with the active layers and each comprise an insulating material between adjacent active layers. Wordlines span through more than one layer of the array, with each of the wordlines comprising a column of memory cell portions coupled via source terminals and drain terminals of column-associated ReRAM elements. Bitlines each span through an associated active layer of the array, with each of the bitlines comprising a row of gate portions coupled via at least gate terminals of row-associated ReRAM elements.

Abstract translation: 为了提供增强的数据存储设备和系统，本文提供了各种系统，体系结构，设备和方法。 在第一个例子中，提供了一种多层电阻随机存取存储器（ReRAM）阵列。 阵列的有源层各自包括多个ReRAM元件，每个ReRAM元件包括具有栅极端子的栅极部分和具有源极端子和漏极端子的存储器单元部分。 阵列的绝缘层与有源层交替并且各自包括相邻有源层之间的绝缘材料。 字线跨越阵列的多于一层，每个字线包括经由列关联的ReRAM元件的源极端子和漏极端子耦接的一列存储器单元部分。 位线各自跨越阵列的相关有源层，每个位线包括至少经由行相关ReRAM元件的栅极端子耦合的一行栅极部分。

公开(公告)号：WO2017189083A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/019168

申请日：2017-02-23

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： BEDAU, Daniel

IPC: H01L27/24

CPC classification number: H01L27/2463 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147

Abstract: An apparatus for high density memory with integrated logic. Specifically, a three terminal resistive random access memory (ReRAM) device having Schottky barriers that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes an insulating layer, a source region disposed on the insulating layer, a drain region disposed on the insulating layer, a binary or complex oxide memory material, a gate dielectric layer, and a gate electrode. As voltage is applied the Schottky barrier breaks down leading to the formation of a conductive anodic filament (CAF). The CAF is non-volatile and short-circuits the reverse-biased barrier thus keeping the device in a low resistance state. Removing the CAF switches the device back to a high resistance state. Thus, a new type of semiconductor device advantageously combines computation and memory further providing for very high density NAND chains.

Abstract translation:

一种集成逻辑的高密度存储器。 具体地，提供了具有可以从低电阻状态切换到高电阻状态的肖特基势垒的三端子电阻随机存取存储器（ReRAM）器件。 肖特基晶体管存储器件包括绝缘层，设置在绝缘层上的源极区，设置在绝缘层上的漏极区，二元或复合氧化物存储材料，栅极电介质层和栅电极。 施加电压时，肖特基势垒击穿导致形成导电阳极丝（CAF）。 CAF是非易失性的，并使反向偏置的屏障短路，从而使器件保持在低电阻状态。 移除CAF会将设备切换回高电阻状态。 因此，新型半导体器件有利地结合了进一步提供非常高密度NAND链的计算和存储器。

公开(公告)号：WO2021101591A1

公开(公告)日：2021-05-27

申请号：PCT/US2020/035915

申请日：2020-06-03

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： BEDAU, Daniel

IPC: G01R33/12 ,  B03C1/01 ,  C12Q1/68

Abstract: Disclosed herein are devices for molecule detection and methods for using detection devices for molecule detection, such as nucleic acid sequencing. In some embodiments, a detection device comprises one or more pole pieces, one or more sensors, each of the one or more sensors coupled to at least one of the one or more pole pieces, and detection circuitry coupled to the one or more sensors. The detection circuitry is configured to detect a characteristic of each of the one or more sensors, the characteristic indicating presence or absence of one or more magnetic nanoparticles (MNPs) coupled to at least one of a plurality of molecules to be detected, and at least one of the one or more pole pieces is operable to draw the one or more MNPs toward at least one of the one or more sensors.

公开(公告)号：WO2021050106A1

公开(公告)日：2021-03-18

申请号：PCT/US2020/023069

申请日：2020-03-17

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： BRAGANCA, Patrick ,  BEDAU, Daniel

IPC: C12Q1/6869 ,  C12Q1/6809

Abstract: Disclosed herein are improved methods and systems for sequencing nucleic acid that exploit the temperature -dependence of the emitted intensity of fluorescent dyes. The temperature of the sequencing reaction is adjusted during each sequencing cycle, and the emission, or lack of emission, of light meeting or exceeding a threshold by the fluorescent dyes at different temperatures, or within different temperature ranges, is used to detect the fluorescent labels of the incorporated dNTPs and thereby sequence the nucleic acid. The disclosed methods enable a determination of the dNTP incorporated at any given site with a reasonable number of chemistry steps without the complex optics necessary for prior-art systems.

公开(公告)号：WO2021252032A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/019302

申请日：2021-02-23

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： BEDAU, Daniel

IPC: G06F3/06 ,  H04L9/08 ,  G06F21/79 ,  G06F13/4282 ,  G06F21/602 ,  H04B10/27 ,  H04L9/0858

Abstract: This disclosure relates to secure optical communication links. In particular, this disclosure relates to data storage devices, random access memories, host interfaces, and network layers that comprise a secure optical communication link. A data storage device comprises an optical data port to connect to an optical communication link external to the data storage device and a non-volatile storage medium to store user content data received over the optical communication link. A controller controls access to the user content data stored on the non- volatile storage medium. A cryptography engine uses a cryptographic key to perform cryptographic operations on data sent and received through the optical data port. An optical key distribution device coupled to the optical data port performs quantum key distribution over the optical communication link to provide the cryptographic key to the cryptography engine.

公开(公告)号：WO2021262252A1

公开(公告)日：2021-12-30

申请号：PCT/US2021/014952

申请日：2021-01-25

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： MA, Wen ,  HOANG, Tung, Thanh ,  BEDAU, Daniel ,  KINNEY, Justin

IPC: H04L12/743 ,  G06F16/903 ,  C12Q1/6869 ,  G16B30/10 ,  G16B40/20

Abstract: A device includes arrays of Non-Volatile Memory (NVM) cells. Reference sequences representing portions of a genome are stored in respective groups of NVM cells. Exact matching phase substring sequences representing portions of at least one sample read are loaded into groups of NVM cells. One or more groups of NVM cells are identified where the stored reference sequence matches the loaded exact matching phase substring sequence using the arrays at Content Addressable Memories (CAMs). Approximate matching phase substring sequences are loaded into groups of NVM cells. One or more groups of NVM cells are identified where the stored reference sequence approximately matches the loaded approximate matching phase substring sequence using the arrays as Ternary CAMs (TCAMs). At least one of the reference sequence and the approximate matching phase substring sequence for each group of NVM cells includes at least one wildcard value when the arrays are used as TCAMs.

公开(公告)号：WO2017218057A1

公开(公告)日：2017-12-21

申请号：PCT/US2017/019747

申请日：2017-02-27

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： BEDAU, Daniel

IPC: H01L45/00 ,  H01L27/24 ,  H01L29/68

CPC classification number: H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/04 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/146

Abstract: A three terminal ReRAM device, which combines a Schottky barrier transistor and a Schottky barrier ReRAM into a single device is provided. The device includes a source region (106), a drain region (108), a gate electrode (114), and a ReRAM material (110) between them, all disposed on an insulating layer (104). The ReRAM material can include a metal oxide, such as zinc or hafnium oxide. A Schottky barrier (118) forms naturally between the drain region and the ReRAM material. As voltage is applied to the gate electrode and the source region, the Schottky barrier breaks down, leading to the formation of a filament (122) across the drain region and the ReRAM material. The filament is non-volatile and short-circuits the reverse-biased barrier, keeping the device in a low resistance state. The filament can be removed by reversing the polarity of the voltage such that the device switches back to a high resistance state.

Abstract translation: 提供了三端子ReRAM器件，其将肖特基势垒晶体管和肖特基势垒ReRAM组合成单个器件。 该器件包括全部设置在绝缘层（104）上的源极区域（106），漏极区域（108），栅极电极（114）以及它们之间的ReRAM材料（110）。 ReRAM材料可以包括金属氧化物，例如锌或氧化铪。 肖特基势垒（118）在漏极区和ReRAM材料之间自然形成。 随着电压施加到栅极电极和源极区域，肖特基势垒击穿，导致在漏极区域和ReRAM材料上形成灯丝（122）。 灯丝是非挥发性的，并使反向偏压屏障短路，使器件保持低电阻状态。 可以通过反转电压的极性来去除灯丝，以便器件切换回高电阻状态。

公开(公告)号：WO2017189082A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/019165

申请日：2017-02-23

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： BEDAU, Daniel

IPC: H01L27/24

CPC classification number: H01L45/1206 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/146

Abstract: The present disclosure generally relates to an apparatus for a three terminal nonvolatile memory cell. Specifically, a three terminal nonvolatile bipolar junction transistor. The bipolar junction memory device includes a collector layer, a base layer disposed on the collector layer, an emitter layer disposed on the base layer, and a conductive anodic filament extending from the collector layer to the base layer. As current is applied to the transistor and a voltage is applied between P-N junction of the collector layer and the base layer, a conductive anodic filament (CAF) forms. The CAF is non-volatile and short circuits the reverse-biased P-N junction barrier thus keeping the device in a low-resistive state. Removing the CAF switches the device back to a high resistive state. Thus, a new type of semiconductor device advantageously combines computation and memory to form a flux-linkage modulated memory cell.

Abstract translation: 本公开一般涉及用于三端子非易失性存储器单元的设备。 具体而言，三端非易失性双极结型晶体管。 双极结存储器件包括集电极层，设置在集电极层上的基极层，设置在基极层上的发射极层以及从集电极层延伸到基极层的导电阳极丝。 当电流施加到晶体管并且在集电极层的P-N结和基极层之间施加电压时，形成导电阳极丝（CAF）。 CAF是非易失性的，将反向偏置的P-N结势垒短路，从而保持器件处于低电阻状态。 移除CAF可将设备切换回高电阻状态。 因此，新型半导体器件有利地将计算和存储器组合在一起以形成磁通调制存储器单元。