US09837584B2
Embodiments of the present invention provide a bluish green phosphor represented by Formula 1 below. In particular, the bluish green phosphor and a light emitting device package including the same may have improved luminescence characteristics and properties due to influence of cations and anions included in a composition formula: AaBbOcNdGeDfEg:REh [Formula 1] wherein A is at least one selected from the group consisting of Be, Mg, Ca, Sr, Ba and Ra elements, B is at least one selected from the group consisting of Si, Ge and Sn elements, G is any one of C, Cl, F and Br elements, D is one element or a mixture type of two or more elements selected from Li, Na and K, E is at least one selected from the group consisting of P, As, Bi, Sc, Y and Lu, RE is at least one selected from the group consisting of Eu, Ce, Sm, Er, Yb, Dy, Gd, Tm, Lu, Pr, Nd, Pm and Ho, 0
US09837579B2
In a method for producing a semiconductor light emitting device: a semiconductor lamination of first and second semiconductor layers having different conductive types is formed; a portion of the semiconductor lamination is removed to expose an area of a surface of the first semiconductor layer; a conductor layer connecting the first and second semiconductor layers is formed; a first electrode is formed on the exposed areas of the first semiconductor layer and a second electrode is formed on an upper surface of the second semiconductor layer; a barrier layer covering at least one of the first and second electrodes is formed; and a connection part in the conductor layer connecting the first and second semiconductor layers is removed.
US09837573B2
The method comprises the steps of providing a semiconductor device comprising a semiconductor layer (1) with at least one radiation sensor (6) and a dielectric layer (2), arranging a web (3) comprising a plurality of recesses (4) on the dielectric layer, and introducing ink of different colors (A, B, C) in the recesses by inkjets (I).
US09837566B2
A photodiode includes a semiconductor substrate, a crystalline layer on the semiconductor substrate, an insulating pattern layer on the crystalline layer to define a plurality of holes exposing a top surface of the crystalline layer, a seed layer in the plurality of holes and directly on the crystalline layer, and a light absorption layer on the seed layer and the insulating pattern layer.
US09837562B2
There is provided a capacitive coupled electodeless plasma apparatus for processing a silicon substrate. The apparatus includes at least one inductive antenna driven by time-varying power sources for providing at least one electrostatic field; and a chamber for locating the silicon substrate. There is also provided a method for processing a silicon substrate using capacitively coupled electrodeless plasma.
US09837558B2
A concentrator photovoltaic module 1M includes a vessel-shaped housing 11 composed of a metal and a flexible printed wiring board 12 provided so as to be in contact with an inner surface of the housing 11. The flexible printed wiring board 12 includes an insulating layer 124, an insulating substrate 121a, a pattern 121b, a plurality of power generation elements 122, and an insulting layer 126. The insulating layer 124 is in contact with a bottom surface 11a of the housing 11. The insulating substrate 121a is provided on the insulating layer 124 and has flexibility. The pattern 121b is composed of a conductor and is provided on the insulating substrate 121a. The plurality of power generation elements 122 are mounted on the pattern 121b. The insulating layer 126 is provided so as to cover an entire surface of the pattern 121b except for portions where the power generation elements 122 are mounted.
US09837550B2
A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer disposed on the substrate that partially overlaps the gate electrode and includes an oxide semiconductor material; and a source electrode and a drain electrode disposed on the semiconductor layer, where the drain electrode is spaced apart from the source electrode. The source electrode and the drain electrode each include a barrier layer and a main wiring layer, the a main wiring layer is disposed on the barrier layer, and the barrier layer includes a first metal layer disposed on the semiconductor layer, and a second metal layer disposed on the first metal layer.
US09837549B2
According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.
US09837545B2
A transistor using an oxide semiconductor, which has good on-state characteristics is provided. A high-performance semiconductor device including the transistor capable of high-speed response and high-speed operation is provided. The transistor includes the oxide semiconductor film including a channel formation region and low-resistance regions in which a metal element and a dopant are included. The channel formation region is positioned between the low-resistance regions in the channel length direction. In a manufacturing method of the transistor, the metal element is added by heat treatment performed in the state where the oxide semiconductor film is in contact with a film including the metal element and the dopant is added through the film including the metal element by an implantation method so that the low resistance regions in which a metal element and a dopant are included are formed.
US09837543B2
The invention provides an oxide semiconductor target including an oxide sintered body including zinc, tin, oxygen, and aluminum in a content ratio of from 0.005% by mass to 0.2% by mass with respect to the total mass of the oxide sintered body, in which the content ratio of silicon to the total mass of the oxide sintered body is less than 0.03% by mass.
US09837541B1
A semiconductor device includes: a gate structure on a substrate; a first doped region adjacent to one side of the gate structure; a second doped region adjacent to another side of the gate structure; and fin-shaped structures on the substrate. Preferably, a number of the fin-shaped structures covered by the gate structure is different from a number of the fin-shaped structures overlapping the first doped region or the second doped region.
US09837539B1
A finFET device and a method of forming are provided. The method includes forming a first dielectric layer over a transistor. The method also includes forming a second dielectric layer over the first dielectric layer. The method also includes forming a first opening in the second dielectric layer to expose at least a portion of a gate electrode of the transistor. The method also includes forming a second opening in the first dielectric layer to expose at least a portion of a source/drain region of the transistor. The second opening is connected to the first opening, and the first opening is formed before the second opening. The method also includes forming an electrical connector in the first opening and the second opening.
US09837532B2
A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure. The source region (41) is located in the well region (34); the drain region (34) is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region (23) and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region (24) and a bottom-layer P-region which are butted vertically.
US09837515B2
A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.
US09837511B2
A method for fabricating semiconductor device includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.
US09837507B1
A field effect transistor includes a channel layer made of a semiconductor and a metal gate structure. The metal gate structure includes a gate dielectric layer, a barrier layer formed on the gate dielectric layer, a work function adjustment layer formed on the barrier layer and made of one of Al and TiAl, a blocking layer formed on the work function adjustment layer and made of TiN, and a body metal layer formed on the blocking layer and made of W. A gate length over the channel layer is in a range from 5 nm to 15 nm, and a thickness of the first conductive layer is in a range of 0.2 nm to 3.0 nm. A range between a largest thickness and a smallest thickness of the first conductive layer is more than 0% and less than 10% of an average thickness of the first conductive layer.
US09837503B2
A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 1017 cm−3 or less. A first insulator surrounds the pillar-shaped semiconductor and a first metal surrounds a portion of the first insulator at a first end of the pillar-shaped semiconductor. A second metal surrounds a portion of the first insulator at a second end of the pillar-shaped semiconductor, and a third metal surrounds a portion of the first insulator in a region between the first and second metals. The first metal and the second metal are electrically insulated from the third metal. Source/drain regions are defined in the pillar-shaped semiconductor due to a work function difference between the pillar-shaped semiconductor and the first and second metals.
US09837500B2
Provided is a semiconductor device. In some examples, the semiconductor device includes an fin active region protruding from a substrate, gate patterns disposed on the fin active region, a source/drain region disposed on the fin active region between the gate patterns, and contact patterns disposed on the source/drain region. The source/drain region may have a protruding middle section, which may form a wave-shaped upper surface of the source/drain region.
US09837494B2
A method for producing a Group III nitride semiconductor comprising forming mesas on a main surface of a substrate, and growing Group III nitride semiconductor in a c-axis direction thereof, wherein the plane most parallel to the side surfaces of the mesas or the dents among the low-index planes of growing Group III nitride semiconductor is a m-plane (1-100), and when a projected vector obtained by orthogonally projecting a normal vector of the processed side surface to the main surface is defined as a lateral vector, an angle between the lateral vector and a projected vector obtained by orthogonally projecting a normal vector of the m-plane of the growing Group III nitride semiconductor to the main surface is 0.5° or more and 6° or less.
US09837492B2
In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.
US09837484B2
A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.
US09837479B2
Embodiments of the invention disclose an array substrate and a fabrication method thereof, and a display device. The array substrate comprises a plurality of pixel units disposed on a base substrate, and the pixel unit comprises a thin-film transistor structure region and a display region other than the thin-film transistor structure region. A thin-film transistor structure is formed in the thin-film transistor structure region, an organic light-emitting diode is formed in the display region, and the thin-film transistor structure is configured to drive the organic light-emitting diode. A light-shielding layer is formed above the thin-film transistor structure in the thin-film transistor structure region, and the light-shielding layer is configured to block a blue light from entering the thin-film transistor structure.
US09837469B1
An example system includes a processing circuit coupled to a memory system and an interface coupled between the processing circuit and a device. The memory system includes a resistive memory array comprising multiple memory structures. Each memory structure comprises a resistive memory cell and is associated with a P-I-N diode. The processing circuit is to access the resistive memory array responsive to a signal received from the device via the interface.
US09837464B2
BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.
US09837451B2
An EL display having high operating performance and reliability is provided. LDD regions 15a through 15d of a switching TFT 201 formed in a pixel are formed such that they do not overlap gate electrodes 19a and 19b to provide a structure which is primarily intended for the reduction of an off-current. An LDD region 22 of a current control TFT 202 is formed such that it partially overlaps a gate electrode 35 to provide a structure which is primarily intended for the prevention of hot carrier injection and the reduction of an off-current. Appropriate TFT structures are thus provided depending on required functions to improve operational performance and reliability.
US09837447B2
A thin film transistor array panel according to an exemplary embodiment of the invention includes: an insulating substrate; a gate line disposed on the insulating substrate and including a gate pad portion; a data line insulated from and crossing the gate line, and including a source electrode and a data pad portion; a drain electrode facing the source electrode; an organic insulating layer disposed on the data line and the drain electrode, and including a first contact hole; a common electrode disposed on the organic insulating layer, and including a second contact hole; a passivation layer disposed on the common electrode, and including a third contact hole; and a pixel electrode disposed on the passivation layer, and being in contact with the drain electrode, in which the third contact hole is disposed to be adjacent to one surface of the first contact hole for improvement of an aperture ratio and a stable electrode connection.
US09837444B2
A display device is described that has reduced resistance in one or more of the gate, common, data electrical lines that control the operation of the pixels of the display device. Reduced resistance is achieved by forming additional metal and/or metal-alloy layers on the gate, common, and/or data lines in such a manner so that the cross-sectional area of those lines is increased. As a consequence, each such line is formed so as to be thicker than could otherwise be achieving without causing defects in the rubbing process of an alignment layer. Additionally, no widening of these lines is needed, thus preserving the aspect ratio of the device. The gate insulating and semiconducting layers that in part make up the thin film transistors that help control the operation of the pixels of the device may also be designed to take into account the increased thickness of the lines.
US09837442B2
An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.
US09837438B2
A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
US09837430B2
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate, the stacked body including a plurality of electrode layers, a plurality of insulating layers, the plurality of insulating layers having a side surface, a plurality of first conductive films provided between the plurality of electrode layers and the plurality of insulating layers, the plurality of first conductive films having a side surface, and a blocking insulating film, the blocking insulating film including a first portion and a second portion; and a semiconductor film. The first distance between the semiconductor film and the side surface of the plurality of first conductive films is shorter than a second distance between the semiconductor film and the second portion.
US09837429B2
A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.
US09837427B2
Deterioration in reliability is prevented regarding a semiconductor device. The deterioration is caused when an insulating film for formation of a sidewall is embedded between gate electrodes at the time of forming sidewalls having two kinds of different widths on a substrate. A sidewall-shaped silicon oxide film is formed over each sidewall of a gate electrode of a low breakdown voltage MISFET and a pattern including a control gate electrode and a memory gate electrode. Then, a silicon oxide film beside the gate electrode is removed, and a silicon oxide film is formed on a semiconductor substrate, and then etchback is performed. Accordingly, a sidewall, formed of a silicon nitride film and the silicon oxide film, is formed beside the gate electrode, and a sidewall, formed of the silicon nitride film and the silicon oxide films, is formed beside the pattern.
US09837425B2
A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.
US09837422B2
A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.
US09837410B1
Semiconductor devices are fabricated with vertical field effect transistor (FET) devices having uniform structural profiles. Semiconductor fabrication methods for vertical FET devices implement a process flow to fabricate dummy fins within isolation regions to enable the formation of vertical FET devices with uniform structural profiles within device regions. Sacrificial semiconductor fins are formed in the isolation regions concurrently with semiconductor fins in the device regions, to minimize/eliminate micro-loading effects from an etch process used for fin patterning and, thereby, form uniform profile semiconductor fins. The sacrificial semiconductor fins within the isolation regions also serve to minimize/eliminate non-uniform topography and micro-loading effects when planarizing and recessing conductive gate layers and, thereby form conductive gate structures for vertical FET devices with uniform gate lengths in the device regions. The sacrificial semiconductor fins are subsequently removed and replaced with insulating material to form the dummy fins.
US09837409B2
A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.
US09837404B2
At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.
US09837401B2
Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.
US09837392B2
An LED lighting apparatus includes an LED substrate, a LED chip, a sealing resin member, and a reflecting face. The LED substrate has a main surface. The LED chip is mounted on the main surface of the LED substrate. The sealing resin member is made of a material that transmits light from the LED chip. The sealing resin member covers the LED chip. The sealing resin member has a shape bulging in the direction in which the main surface faces. The reflecting face surrounds the sealing resin member.
US09837388B2
A display device according to an embodiment of the present disclosure may include a lower substrate disposed with a line electrode at an upper portion thereof, a plurality of semiconductor light emitting devices electrically connected to the line electrode to generate light, a wavelength converter disposed on the semiconductor light emitting device to convert a wavelength of light generated from the semiconductor light emitting device, and a conductive adhesive layer comprising conductors configured to electrically connect the lower substrate to the semiconductor light emitting device and a body configured to surround the conductors, wherein the semiconductor light emitting device has a composition formula of InxAlyGa1-x-yN (0≦x≦1, 0≦y≦1, 0≦x+y≦1).
US09837385B1
A package includes a chip, a wire, a mold layer and a redistribution layer. The chip includes a conductive pad. The wire is bonded to the conductive pad of the chip. The mold layer surrounds the first chip and the wire. The redistribution layer is disposed on the mold layer and contacts an exposed portion of the wire.
US09837380B2
A semiconductor device includes a device carrier, a first semiconductor chip mounted on the device carrier and a second semiconductor chip mounted on the device carrier. Further, the semiconductor device includes a first contact clip bonded to a first electrode of the first semiconductor chip, a second contact clip bonded to a first electrode of the second semiconductor chip and an insulating connector configured to hold the first contact clip and the second contact clip together.
US09837379B2
A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
US09837378B2
A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.
US09837377B2
A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area and a second area that is provided independently from the first area, the first area including a first circuit formed in the first area, and the second area including a second circuit formed in the second area.
US09837376B2
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
US09837375B2
A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.
US09837356B1
Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction product of a metal or metal alloy of an interconnect metallic region with a metal of either a metal cap or a metal layer. In some embodiments, the metal cap may include a metal nitride and thus a nitride-containing intermetallic compound can be formed. The formation of the intermetallic compound can improve the electromigration resistance of the interconnect structures and widen the process window for fabricating interconnect structures.
US09837353B2
A semiconductor structure is disclosed that includes a semiconductor structure includes an active area, a first conductive line, a conductive via, a first conductive metal segment coupled to the conductive line through the conductive via, a second conductive metal segment disposed over the active area, and a local conductive segment configured to couple the first conductive metal segment and the second conductive metal segment.
US09837348B2
A device includes a dielectric layer, a passive device including a portion in the dielectric layer, and a plurality of voids in the dielectric layer and encircling the passive device.
US09837334B2
Cooling devices for SOI wafers and methods for forming the devices are presented. A substrate having a top surface layer, a support substrate and an insulator layer isolating the top surface layer from the support substrate is provided. At least one device is disposed in the top surface layer of the substrate. The IC includes a cooling device. The cooling device includes a doped layer which is disposed in a top surface of the support substrate, and a RDL layer disposed within the support substrate below the doped layer for providing connections to hotspots in the doped layer to facilitate thermoelectric conduction of heat in the hotspots away from the hotspots.
US09837332B2
A heat spreading lid including a lid body and a wing portion having a thermal interface material disposed on the wing portion such that the wing portion flexibly moves with the thermal interface material independently from the lid body.
US09837329B2
The present application relates to a cured product and the use thereof. When the cured product, for example, is applied to a semiconductor device such as an LED or the like, the decrease in brightness may be minimized even upon the long-term use of the device, and since the cured product has excellent cracking resistance, the device having high long-term reliability may be provided. The cured product has excellent processability, workability, and adhesive properties or the like, and does not cause whitening and surface stickiness, etc. Further, the cured product exhibits excellent heat resistance at high temperature, gas barrier properties, etc. The cured product may be, for example, applied as an encapsulant or an adhesive material of a semiconductor device.
US09837323B2
The present disclosure provides a method for forming a semiconductor structure. The method includes providing a semiconductor substrate; forming a first active region, a second active region, a third active region, and a fourth active region in the semiconductor substrate; and forming a middle-voltage P well region (MVPW) in each of the first active region and the second region simultaneously and forming a middle-voltage N well (MVNW) region in each of the third active region and the fourth active region simultaneously.
US09837320B2
First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.
US09837319B2
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
US09837306B2
An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.
US09837301B2
A method for producing hybrid substrates which can be incorporated into a semiconductor production line involves: forming an ion-injection region (3) by injecting ions from the surface of a silicon substrate (1); adhering the ion-injection surface of the silicon substrate and the surface of a sapphire substrate (4) to one another directly or with an insulating film (2) interposed therebetween; and then obtaining a hybrid substrate (8) having a silicon thin-film (semiconductor layer; 6) on the sapphire substrate (4), by detaching the silicon substrate (1) in the ion-injection region (3). This method is characterized in that the adhering to the silicon substrate (1) occurs after the sapphire substrate (4) is heat-treated in advance in a reducing atmosphere.
US09837300B2
A semiconductor substrate and a base substrate are prepared; an oxide film is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form a separation layer at a predetermined depth from a surface of the semiconductor substrate; a nitrogen-containing layer is formed over the oxide film after the ion irradiation; the semiconductor substrate and the base substrate are disposed opposite to each other to bond a surface of the nitrogen-containing layer and a surface of the base substrate to each other; and the semiconductor substrate is heated to cause separation along the separation layer, thereby forming a single crystal semiconductor layer over the base substrate with the oxide film and the nitrogen-containing layer interposed therebetween.
US09837293B2
Embodiments of mechanisms for charging a gas into a cassette pod are provided. A method for charging a gas into a cassette pod includes loading at least one semiconductor wafer into a housing of the cassette pod after the at least one semiconductor wafer is processed by a processing apparatus. The method also includes removing the cassette pod from the processing apparatus by a transporting apparatus to a predetermined destination. The method further includes charging a gas into an enclosure in the housing of the cassette pod from a gas supply assembly disposed on the housing.
US09837284B2
A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity.
US09837282B1
A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.
US09837278B2
A semiconductor structure includes a die including a top surface and a sidewall, and a molding surrounding the die and including a top surface, a sidewall interfacing with the sidewall of the die, and a curved surface including a curvature greater than zero and coupling the sidewall of the molding with the top surface of the molding.
US09837275B2
This invention involves a fabrication method of fast recovery diode, which includes following steps: growing a sacrificial oxide layer on a surface of an N− substrate; forming a P type doped field-limiting ring region on the substrate; forming a P type doped anode region on the substrate; removing the sacrificial oxide layer; annealing the substrate to form a PN junction; implanting oxygen into the surface of the substrate by ion implantation; annealing the substrate to form a silicon dioxide layer on the surface of the substrate; removing the silicon dioxide layer; forming an anode electrode and a cathode electrode of the fast recovery diode. The method eliminates the curved parts near the silicon surface of the profile of PN junction, decreases electric field intensity at the surface of the substrate, therefore increases the breakdown voltage and reliability of the fast recovery diode.
US09837273B2
A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.
US09837263B2
A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle having a SiN sub-cycle and a SiCN sub-cycle. The SiN sub-cycle can include alternately and sequentially contacting the substrate with a silicon precursor and a SiN sub-cycle nitrogen precursor. The SiCN sub-cycle can include alternately and sequentially contacting the substrate with carbon-containing precursor and a SiCN sub-cycle nitrogen precursor. The SiN sub-cycle and the SiCN sub-cycle can include atomic layer deposition (ALD). The process for depositing the silicon carbon nitride film can include a plasma treatment. The plasma treatment can follow a completed plurality of complete deposition cycles.
US09837255B2
Applications of ion-ion reaction chemistry are disclosed in which proton transfer reactions (PTR) are used to (1) simplify complex mixture analysis of samples introduced into a mass spectrometer, and (2) improve resolution and sensitivity for the analysis of large proteins in excess of 50 kDa by removing charge and reducing the collisional cross section.
US09837253B2
The invention is directed at sputter targets including 50 atomic % or more molybdenum, a second metal element of titanium, and a third metal element of chromium or tantalum, and deposited films prepared by the sputter targets. In a preferred aspect of the invention, the sputter target includes a phase that is rich in molybdenum, a phase that is rich in titanium, and a phase that is rich in the third metal element.
US09837245B2
Disclosed herein is a micro stage using a piezoelectric element that can be reliably operated even in a vacuum environment. In a particle column requiring a high precision, for example, a microelectronic column, the micro stage can be used as a stage with micro or nano degree precision for alignment of parts of the column, or for moving a sample, and so on.
US09837243B2
An ion pump and a charged particle beam device each includes two opposite flat-plate cathodes, an anode with a cylindrical shape having openings that face the respective flat-plate cathodes, a voltage application unit configured to apply a potential higher than potentials of the flat-plate cathodes to the anode, a magnetic field application unit configured to apply a magnetic field along an axial direction of the cylindrical shape of the anode, and a cathode bar arranged within the anode. The surface of the cathode bar is formed with a material that forms a non-evaporative getter alloy film on the anode or the flat-plate cathodes.
US09837238B2
A photocathode designs that leverage the grazing incidence geometry yield improvements through the introduction of recessed structures, such as cones, pyramids, pillars or cavities to the photocathode substrate surface. Improvements in yield of up to 20 times have been shown to occur in grazing incidence geometry disclosed herein due to a larger path length of the X-ray photons which better matches the secondary electron escape depth within the photocathode material. A photocathode includes a substrate having a first side and a second side, the first side configured to receive x-ray energy and the second side opposing the first side. A structured surface is associated with the second side of the substrate such that the structured surface includes a plurality of recesses from the second side of the substrate into the substrate.
US09837233B2
A rotating dual break point contact includes a rotor support, a first shaft, a second shaft, a third shaft, a first connection rod, a second connection rod, a contact bridge and a contact spring. The contact bridge is provided in the rotor support, and the contact bridge rotates relative to the rotor support by means of the first shaft, the second shaft, the third shaft, the first connection rod and the second connection rod. The contact bridge rotates between an initial pressure position and a maximum repulsion position. A single contact spring is mounted on one side of the contact bridge and is located in the rotor support.
US09837225B2
An electrical snap on switch includes a pair of associated contact elements, the contact elements include a fixed contact element and a movable contact element arranged facing the fixed contact element and that may come into contact with the fixed contact element for establishing a first conductive path. The snap on switch may also include a snap-action switching device that includes a tilting driving member pivotally mounted around a horizontal axis between an upper position and a lower position. The movable contact element is a movable portion of an elastically deformable conductive blade. The driving member includes a cam, which cooperates with a cam follower portion of the blade to deform or relax the blade, to cause the movable contact to come into contact, or out of contact, with the fixed contact element, therefore to realize switching.
US09837224B2
A load or a generator is connected to an energy line, e.g. a ring feeder of an energy distribution network by using a switching system. For this purpose, the switching system has a thyristor circuit, which is connected in parallel to a disconnect switch and connects the transformer of the switching system to an energy line. Thereby an efficient disconnect switch can be realized, which can be dimensioned depending on the power of the load or generator.
US09837223B2
A touch panel includes: a body connected to wiring drawn out to the outside of the touch panel; a sheet member to which decoration printing is added; an adhesive that pastes the sheet member on the body and is the same size as the sheet member; and a non-adhesion film formed between the adhesive and the wiring.
US09837221B2
A key switch includes a baseplate, a circuit layer, a keycap and a support rod. The baseplate has a hook and a first through hole neighboring to the hook. The circuit layer includes a first sublayer disposed above the baseplate and having a second through hole, and a second sublayer disposed above the first sublayer and having a third through hole; a portion of the second sublayer extends over the second through hole and forms a first resilient portion; the first resilient portion has four sides, two of which connect to the second sublayer; and the first resilient portion is neighboring to the hook. The keycap is disposed above the baseplate and can move upward and downward in respect to the baseplate. The support rod has a first portion and a second portion; the first portion movably connects to the keycap and the second portion engages the hook.
US09837215B2
A multilayer ceramic capacitor may include a ceramic body including a plurality of dielectric layers; a first internal electrode disposed in the ceramic body and exposed to a first side surface in a width direction of the ceramic body and a second internal electrode disposed in the ceramic body and exposed to the first side surface in the width direction of the ceramic body; and first to third external electrodes disposed on the first side surface in the width direction of the ceramic body.
US09837213B2
In an embodiment of a ceramic electronic component, an external electrode 12 of a capacitor 10 has one first planar part SEa of roughly rectangular profile positioned on a surface that specifies the length dimension of the ceramic chip 11, as well as four second planar parts SEb of roughly rectangular profile positioned on both surfaces that specify the height dimension, and both surfaces that specify the width dimension, of the ceramic chip 11 and also continuing to the first planar part SEa. The second planar part SEb is constituted by a baked metal film 12a formed on the exterior surface of the ceramic chip 11 and a plated metal film 12b formed on the exterior surface of the baked metal film 12a via an adhesive force mitigation film 12c.
US09837211B2
A thin film capacitor comprises a base material, a dielectric layer provided on the base material, and an upper electrode layer provided on the dielectric layer. The dielectric layer includes a plurality of columnar crystals that extend along a normal direction with respect to a surface of the upper electrode layer. The columnar crystal has a perovskite crystal structure represented by AyBO3. An element A is at least one of Ba, Ca, Sr, and Pb, and an element B is at least one of Ti, Zr, Sn, and Hf. Further, y≦0.995 is satisfied, and the dielectric layer contains 0.05 to 2.5 mol of Mg per 100 mol of AyBO3.
US09837210B2
A laminated ceramic capacitor having internal electrodes configured such that Sn is dissolved in Ni, and, in a region of each of the internal electrodes at a depth of 2 nm from a surface thereof facing a ceramic dielectric layer, a CV value representing variation of a Sn/(Ni+Sn) ratio (ratio of number of atoms) is less than or equal to 32%. As a conductive paste for forming the internal electrodes, a conductive paste containing a Ni powder and a tin oxide powder which is represented by SnO or SnO2 and has a specific surface area of more than or equal to 10 m2/g as determined by a BET method is used, or a conductive paste containing a Ni—Sn alloy powder is used, or a conductive paste containing a Ni—Sn alloy powder and a tin oxide powder which is represented by SnO or SnO2 and has a specific surface area of more than or equal to 10 m2/g is used.
US09837205B2
An electromagnetic connector is disclosed that is configured to form a first magnetic circuit portion comprising a first core member and a first coil disposed of the first core member. The electromagnetic connector is configured to mate with a second electromagnetic connector, where the second electromagnetic connector is configured to form a second magnetic circuit portion comprising a second core member and a second coil disposed of the second core member. The first core member and the second core member are configured to couple the first coil to the second coil with a magnetic circuit formed from the first magnetic circuit portion and the second magnetic circuit portion when the electromagnetic connector is mated with the second electromagnetic connector. The magnetic circuit is configured to induce a signal in the first coil when the second coil is energized.
US09837197B2
A linear actuator (20, 20′, 20″) comprises a plunger receptacle (22); a coil (24); a magnetic plunger (26); a magnetic base (28); a return spring (30); and a lock spring (32, 32′). The coil (24) is wound about at least a portion of an exterior surface of the plunger receptacle (22). The magnetic plunger (26) is at least partially disposed within a cavity at least partially formed by an interior surface of the plunger receptacle (22) for linear motion along a plunger axis (34). The magnetic base (28) is radially disposed relative to the plunger (26). The return spring (30) is disposed to bias the plunger (26) to a plunger extended position. The lock spring (32, 32′) is configured and oriented to lock the plunger (26) in the plunger extended position when power is not applied to the coil (24) but to be attracted to the magnetic base (28) and thereby permit movement of the plunger (26) to a plunger retracted position when the power is applied to the coil (24).
US09837172B2
A pointer needle for an indication device of a motor vehicle has a transparent optical waveguide that receives light propagating along a direction of propagation at a light-entry side, and emits the light in an emission direction at a light-exit side. The optical waveguide has a scattering side opposite to the light-exit side, the scattering side having steps arranged offset to one another across the propagation direction. When the steps are irradiated by light, the pointer needle provided in the indication device can clearly be perceived in the dark.
US09837163B2
One embodiment includes obtaining programming order information for the memory area from a first table based on address information. The programming order information indicates an order in which the memory area was programmed. The embodiment further includes determining an estimated elapsed time by accessing a second table based on the obtained programming order information. The estimated elapsed time indicating time that has elapsed since the portion of the memory area was last programmed. The embodiment includes controlling the memory based on the estimated elapsed time.
US09837159B2
Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.
US09837158B2
A nonvolatile memory device includes a memory cell, and a switching unit. The memory cell includes a cell transistor having a floating gate and a coupling capacitor connected to the floating gate. The switching unit is coupled between the coupling capacitor and a bias terminal, and switches on or off based on the comparison result between a cell current flowing through the memory cell with a reference current during a program operation for programming the memory cell.
US09837153B1
Technology is described for selecting a group of reversible-resistance memory cells in which to store data based on information regarding switching the reversible-resistance memory cells from a first resistance state in which the reversible-resistance memory cells are in immediately after fabrication to a second resistance state for the first time after fabrication. Information regarding switching the reversible-resistance memory cells from the first resistance state to the second resistance state for the first time after fabrication may provide insight into factors including, but not limited to, endurance and data retention. In one aspect, a control circuit is configured to select a group of reversible-resistance memory cells in which to store data based on both the difficulty in switching from the first resistance state to the second resistance state for the first time after fabrication and a temperature of the data to be stored in the memory system.
US09837150B2
A nonvolatile memory device includes a nonvolatile memory cell and a variable resistive load portion. The variable resistive load portion is coupled between a bit line of the nonvolatile memory cell and a supply voltage line. The variable resistive load portion is suitable for changing a resistance value between the bit line and the supply voltage line according to a level of a supply voltage applied to the supply voltage line.
US09837138B1
A semiconductor device may be provided. The semiconductor device may include an input signal generator configured to enable an input signal although a reset signal is disabled after a clock enable signal is enabled. The semiconductor device may include a self-refresh enable signal generator configured to generate a self-refresh enable signal based on the input signal.
US09837136B2
A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition.
US09837135B2
A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.
US09837130B2
In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.
US09837129B2
Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools.
US09837113B2
A stationary portion of a spindle motor includes a stator portion and an outside surface. The stator portion includes a stator core and coils. The outside surface extends in an axial direction parallel or substantially parallel to a central axis, and is centered on the central axis. The spindle motor includes a fixing portion at which an inside surface of the stator core and the outside surface are fixed to each other. The fixing portion includes a first press fit portion, a second press fit portion, and a gap arranged therein. The gap is located between the first press fit portion and the second press fit portion. The second press fit portion is located above the first press fit portion. At least a portion of the second press fit portion is located above a middle of the stator core in the axial direction.
US09837105B2
A magnetoresistive element according to an embodiment includes: a first magnetic layer, a second magnetic layer, and an intermediate layer disposed between the first magnetic layer and the second magnetic layer, the intermediate layer including: a first layer containing oxygen and at least one element of Cu, Au, and Ag; and a second layer containing Mg and oxygen, the second layer being disposed between the first layer and the second magnetic layer.
US09837089B2
A device for signal processing includes a receiver and a high-band excitation signal generator. The receiver is configured to receive a parameter associated with a bandwidth-extended audio stream. The high-band excitation signal generator is configured to determine a value of the parameter. The high-band excitation signal generator is also configured to select, based on the value of the parameter, one of target gain information associated with the bandwidth-extended audio stream or filter information associated with the bandwidth-extended audio stream. The high-band excitation signal generator is further configured to generate a high-band excitation signal based on the one of the target gain information or the filter information.
US09837084B2
A speech-synthesizing device includes a hierarchical prosodic module, a prosody-analyzing device, and a prosody-synthesizing unit. The hierarchical prosodic module generates at least a first hierarchical prosodic model. The prosody-analyzing device receives a low-level linguistic feature, a high-level linguistic feature and a first prosodic feature, and generates at least a prosodic tag based on the low-level linguistic feature, the high-level linguistic feature, the first prosodic feature and the first hierarchical prosodic model. The prosody-synthesizing unit synthesizes a second prosodic feature based on the hierarchical prosodic module, the low-level linguistic feature and the prosodic tag.
US09837083B1
A voice controlled assistant has a housing to hold one or more microphones, one or more speakers, and various computing components. The housing has an elongated cylindrical body extending along a center axis between a base end and a top end. The microphone(s) are mounted in the top end and the speaker(s) are mounted proximal to the base end. The microphone(s) and speaker(s) are coaxially aligned along the center axis. The speaker(s) are oriented to output sound directionally toward the base end and opposite to the microphone(s) in the top end. The sound may then be redirected in a radial outward direction from the center axis at the base end so that the sound is output symmetric to, and equidistance from, the microphone(s).
US09837082B2
An interactive server and a controlling method thereof are provided. The method of controlling an interactive server includes receiving data corresponding to a user voice from a user terminal, determining an utterance type of the user voice, in response to determining that the utterance type of the user voice is an integrated utterance type, generating a search response and a chatting response in response to the user voice and generating an integrated response by combining the generated search response and the generated chatting response, and transmitting the generated integrated response to the user terminal.
US09837064B1
A communication device includes a loudspeaker to transmit sound into a room. A signal having a white noise-like frequency spectrum spanning a frequency range of human hearing is generated. Auditory thresholds of human hearing for frequencies spanning the frequency range are stored. Respective levels of background noise in the room at the frequencies are determined. The white noise-like frequency spectrum is spectrally shaped to produce a shaped frequency spectrum having, for each frequency, a respective level that follows either the auditory threshold or the level of background noise at that frequency, whichever is greater. The shaped frequency spectrum is transmitted from the loudspeaker into the room.
US09837054B1
HEADPIECE TUNER is integrated into the nut arrangement of a traditional headless musical instrument featuring lever-based individual string clamps, a removable nut, a truss rod adjustment feature and multi-function cross bar handle. A Magnetic Tuner comprising at least one of two magnetic elements secured to a tremolo, in fulcrum tremolos, moveable therewith about the tremolo pivot axis, in a mechanism operable to provide a first force of tension comprising the traditional tremolo coil spring biasing element and/or, in the case of coil spring integrated tremolo stabilizers, provide a second force of tension to enforce the tremolo at the equilibrium point or initial position.
US09837052B2
A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
US09837049B2
A visible light communication system includes: an illumination device which emits visible light including identification information; an information presentation apparatus which presents information to a person in a range illuminated by the visible light; an information terminal which receives visible light identification information; and an information recording medium which holds pairing information associating the identification information identifying the illumination device with connection information required for connection via wireless communication with the information presentation apparatus. When the information terminal is illuminated by the visible light, the information terminal refers to the pairing information held in the information recording medium to identify the connection information associated with the identification information included in the visible light, and establishes connection with the information presentation apparatus based on the identified connection information.
US09837045B2
A display device includes a display panel; and a display panel driver driving the display panel. The display panel driver includes: a processing circuit configured to perform digital arithmetic processing on R, G and B grayscale values of input image data to calculate R, G and B grayscale values of output image data, respectively, and a control point data generation circuit configured to: generate first control point data indicating the shape of a desired gamma curve; calculate Re, G and B control point data indicating input-output curves of digital arithmetic processing performed on the R, G and B grayscale values of the input image data by correcting the first control point data in response to the input image data. The processing circuit is configured to calculate the R, G and B grayscale values of the output image data in response to the R, G and B control point data.
US09837043B1
A mobile device has a display, one or more processors, and first memory storing instructions for execution by the one or more processors. The mobile device is configured to dock in a headset to form a head-mounted display. A near-field-communication (NFC) channel is established with a tag in the headset, the tag including second memory that stores one or more configuration parameters for the headset. The one or more configuration parameters are received from the tag via the NFC channel. Using the one or more configuration parameters for the headset, the mobile device renders virtual-reality images and displays the rendered virtual-reality images.
US09837036B2
A gate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.
US09837035B2
A liquid crystal display including a display panel having data link lines, data lines, scan lines, and pixels connected to the data lines and the scan lines, a source drive integrated circuit configured to supply data voltages to the data lines via the data link lines, and a scan driver configured to provide scan signals to the scan lines. A p-th (p is a positive integer) data link line is connected to a (p+1)-th data line, and a (p+1)-th data link line is connected to a p-th data line.
US09837031B2
An apparatus and method for driving an LCD device is disclosed to obtain rapid response speed and to enhance picture quality, in which the apparatus includes a liquid crystal panel that includes liquid crystal cells formed in areas defined by gate and data lines; a gate driver that supplies a scan pulse to the gate lines; a timing controller that modulates source data supplied from the external to modulated data for a rapid response speed of liquid crystal cell, and generates discrimination signals by comparing source data of a current frame with uppermost and lowermost gray scales of source data based on whether source data of a current frame is the same as source data of a previous frame or not; and a data driver that converts the modulated data into a video signal by using a plurality of gamma voltages including a first modulation voltage that is higher than an maximum gamma voltage or a second modulation voltage that is lower than a minimum gamma voltage, and supplies the video signal to the data lines.
US09837028B2
A liquid crystal display panel and a liquid crystal display comprising the same are disclosed. The liquid crystal display panel comprise: a plurality of pixels configured in an array, which is formed by a plurality of data lines and a plurality of scan lines that are arranged perpendicularly with respect to the plurality of data lines. The plurality of scan lines comprise: at least two scan lines arranged in correspondence with each line of pixels, the at least two scan lines being alternately connected to each successive pixel located in a corresponding line, wherein each line of pixels is scanned in a plurality of individual time periods. During each time period, when pixel drive signals are input into pixels connected to one of the at least two scan lines via corresponding data lines, the sum of the variation of the pixel drive signals and the variation of input signals of data lines corresponding to pixels connected to the rest of the at least two scan lines equals 0, so that a common electrode voltage will not deviate from a pre-determined voltage. As a result, the phenomenon of deviation generated due to couplings of the common-electrode voltage to data lines can be largely relieved, thus eliminating the phenomenon of horizontal crosstalk caused thereby in the prior art.
US09837025B2
An organic light-emitting diode (OLED) display and method of driving the same are disclosed. In one aspect, the OLED display includes a display panel including a plurality of pixels and a data driver configured to apply a data signal to the display panel in one of two-dimensional (2D) and stereoscopic display modes. The display also includes a controller configured to convert an image signal to 2D image data for the pixels at each of N×k sub-fields in the 2D display mode and convert the image signal to stereoscopic image data for the pixels at each of N sub-fields in the stereoscopic display mode, where N and k are integers greater than 1. The display further includes a frame memory configured to store the 2D image data in the 2D display mode and the stereoscopic image data in the stereoscopic display mode.
US09837023B2
In a pixel circuit, TFTs are connected and driven such that a threshold voltage Vth of a TFT, which is a drive transistor, can be held in a threshold holding capacitor having a capacitance value c1, voltages, including a data potential Vdata representing an image to be displayed, can be held in a data holding capacitor having a capacitance value c2, and charges in the data holding capacitor and the threshold holding capacitor are redistributed at the time of light emission. As a result, a potential obtained by multiplying the data potential Vdata by c1/(c1+c2) is provided to a gate potential of the TFT.
US09837020B2
Embodiments of systems and methods for power control in an Organic Light Emitting Diode (OLED) display device are described. In an embodiment, a method includes monitoring a level of current draw from an Organic Light Emitting Diode (OLED) display device. The method may also include comparing the level of current draw to a threshold value. Additionally, a method may include throttling system power consumption in response to the level of current draw exceeding the threshold value.
US09837019B2
A pixel circuit, an organic electroluminescent display panel and a display device, in a reset and compensation phase, a charge control module of the pixel circuit makes a data signal end and the first input end of a reset control module switch on, and the reset control module resets the control end and a output end of a drive module and compensates reference voltage; in a data writing phase, the charge control module writes the data signal inputted by the data signal end to the first input end of the reset control module; in a light-emitting phase, a light-emitting control module makes the output end of the drive module and the input end of the light emitting device switch on and drives the light emitting device to emit light by integrating the data signal inputted into the drive module with the reference voltage signal compensated into the drive module, which realizes the effect that the drive current driving the light emitting device to emit light is irrelevant to the power supply voltage signal, eliminates the influence on luminous brightness of the light emitting device caused by IR drop of the power supply voltage signal inputted into the pixel circuits, and further guaranteeing the display effect of the display panel.
US09837013B2
Aspects of the present invention are related to systems and methods for compressing display non-uniformity correction data and for using compressed display non-uniformity correction data. A correction image may be compressed by fitting a data model to the correction image data and encoding the model parameter values. A correction image may be decomposed into two images: an image containing the vertically and horizontally aligned structures of the correction image and a smoothly varying image. The smoothly varying image may be compressed by fitting a data model to the smoothly varying image data. Multiple correction images may be compressed by determining eigenvectors which describe the distribution of the multiple correction images. Projection coefficients may be determined by projecting each correction image the determined eigenvectors, and an eigen-image associated with an eigenvector may be compressed. Correction data for a display may be reconstructed from parameter values stored on a display system. A plurality of correction images may be reconstructed from encoded eigen-images stored on a display system.
US09837010B2
A display apparatus is disclosed. The display apparatus may include a mode determining unit, which determines an operation mode of the display apparatus between a first mode and a second mode; a display unit, which includes n scan lines including first through nth scan lines; data lines; and pixels, wherein a pixel is associated with a respective scan line and a respective data line; a gate driver to output scan signals to the scan lines; and a source driver to output data signals to the data lines in synchronization with the scan signals, wherein the gate driver substantially simultaneously outputs the scan signals to an ith scan line and a (k+i)th scan line among the scan lines in the first mode, and k is a positive integer, n is equal to 2k, and i is a positive integer smaller than or equal to k.
US09837007B2
Disclosed is an in-cell touch liquid crystal display (LCD) apparatus comprising: an active area in which a plurality of pixels are provided; and a pad area in which an auto probe test pattern is disposed, wherein the auto probe test pattern comprises a common voltage enable signal line; a common voltage switching unit; a data enable signal line through which a data enable signal is applied; and a data switching unit that is coupled to the data enable signal line and configured to be turned on by the data enable signal and output a data voltage. The common voltage enable signal line and the data enable signal line are disposed separately from each other.
US09837005B2
A detection circuit and a detection method for liquid crystal display are provided. The detection circuit comprises a gate driver for providing row scan signal to liquid crystal cell to be detected; a signal source for providing polarity inversion signal to source driver; a source driver for performing digital-analog conversion on received display data signal according to preset reference voltage and polarity inversion signal, generating pixel voltage signal, and sending pixel voltage signal to liquid crystal cell to be detected. The polarity inversion signal comprises column polarity inversion signals each of which polarity inversion signal is continuous high level signal or continuous low level signal. The polarity inversion mode is a column inversion, which makes white dot of damaged area of alignment film is more prominent during detection process, so it would be easy for the operator to recognize it and avoid the issue of missing detection.
US09837004B2
An apparatus for warning a slippery surface is provided that includes a light emitting device, a mounting unit and a light-refracting liquid or powder to be added to a cleaning solution or other fluid causing a slippery surface. The apparatus is used for the purpose of alerting people in the vicinity of a potential safety hazard of the existence of such safety hazard. The light emitted from the light emitting device is directed toward the slippery surface imbued with light-refracting liquid or powder for the purpose of showing persons the existence of a slippery surface or hazardous condition.
US09837000B2
A sign apparatus of the present disclosure includes a light source operable to emit light, a front panel having a front portion and a side portion, and a rear panel attached to the front panel and having a back portion, a side portion and a rim portion. The rear panel and the front panel define a cavity where the light source is housed. The side portion of the front panel extends between the cavity and the side portion of the rear panel, and the rim portion of the rear panel is configured to follow a contour of the front panel, extend beyond a periphery of the front panel, and have opaque properties.
US09836999B2
A backlighting system for a cabinet sign may include a plurality of panels. Each panel includes a plurality of light emitting diodes (“LEDs”) attached to the panel. The diode has a box sign depth factor of less than about 1.4. An integrated circuit may also be located on the panel. A wire physically connects adjacent panels.
US09836988B2
A remotely actuated emergency medical services training apparatus designed to simulate a moving ambulance. The apparatus is comprised of a mock up of the rear of an ambulance positioned on a set of suspension parts controlled by a computer. A lower base and an upper base are connected via a set of air springs, shock absorbers, and sway braces. The upper base is connected to the mock up of the ambulance. Air springs which move the upper base relative to the lower base are controlled by a set of programmed instructions resident on the computer or manually by a joystick controller connected to the computer. Each component of the apparatus is sized to be easily transported through typically dimensioned doorways and hallways such that assembly and disassembly within the confines of a typical classroom is possible.
US09836986B2
Methods, systems, and devices for dynamic response entry are disclosed herein. In some embodiments, a dynamic response entry system can include a user device that can be a proctor device or a testee device. The testee device can display a list to a testee for a predetermined time period. After the passing of the predetermined time period, the displaying of the list to the testee can be terminated. The testee can provide response to one or several questions, which responses can be input into the proctor device. The input responses can be evaluated and categorized and displayed according to the evaluation and categorization.
US09836984B2
Embodiments provide techniques for dynamically creating a story for playback using a plurality of storytelling devices. Embodiments identify a plurality of storytelling devices available to participate in a storytelling experience. User input associated with the storytelling experience is received. Embodiments further include retrieving a story template based at least in part on the identified plurality of storytelling devices. Additionally, embodiments dynamically create a first story by mapping actions from the retrieved story template to storytelling devices in the plurality of storytelling devices, based at least in part on the received user input, such that the plurality of storytelling devices will perform a respective one or more actions during playback of the first story based on the mapped actions from the retrieved story template.
US09836980B2
Systems, methods, and computer readable media to improve the operation of graphics systems are described. In general, collision avoidance techniques are disclosed that operate even when the agent lacks a priori knowledge of its environment and is, further, agnostic as to whether the environment is two-dimensional (2D) or three-dimensional (3D), whether the obstacles are convex or concave, or whether the obstacles are moving or stationary. More particularly, techniques disclosed herein use simple geometry to identify which edges of which obstacles an agent is most likely to collide. With this known, the direction of an avoidance force is also known. The magnitude of the force may be fixed, based on the agent's maximum acceleration, and modulated by weighting agents.
US09836975B2
An apparatus and method for implementing an exception to a parking restriction, the exception being a parking area defined by one or more coordinates, includes monitoring an area including the parking area; detecting a vehicle in the monitored area; determining whether the detected vehicle is positioned within the parking area; and determining whether the vehicle has permission to park in the parking area. The parking area is not marked on the road.
US09836974B2
An operation management center divides an operation area in which an on-demand bus operates into a plurality of predetermined sub-areas, and searches for candidate routes on which the on-demand bus travels for each divided sub-area. The center sets one of the retrieved routes as a basic route, and sets, as adjustment time for each divided sub-area, time required when the bus passes through a location separated from the basic route. Thus, by setting such adjustment time for each sub-area, and by using the adjustment time set for each sub-area, the center can determine an operation plan that takes into account an additional request while reducing an impact on the determined operation plan.
US09836971B2
Systems for heads-up display of transit industry vehicle information is provided. Information originating from various transit agency systems and arriving at transit industry vehicles may be selectively displayed on a heads-up display. Control and configuration of the information displayed on a heads-up display may be determined by a transit agency and may relate to data displayed on on-board mobile data terminals.
US09836963B1
A mobile device configured to receive telematics data from another vehicle when the mobile device is traveling in a moving vehicle and take corrective action when a travel event exists may be provided. The mobile device may receive telematics data associated with an originating vehicle, analyze the telematics data, and determine or identify that a travel event associated with the originating vehicle exists and, when the travel event is determined to exist, determine whether the travel event is relevant to the moving vehicle or a route that the moving vehicle is presently traveling, and if so, direct corrective action such that safer vehicle travel for the moving vehicle is facilitated based upon the telematics data that is collected by the originating vehicle. An insurance provider may collect an insured's usage of the vehicle safety functionality to calculate, update, and/or adjust insurance premiums, rates, discounts, points, or programs.
US09836959B1
A pedestrian safety system for a restaurant having a drive-through lane for an automobile, a pickup window, and a pedestrian door. The system includes lane sensors proximate the pickup window that generate lane data indicate of the proximity and motion of an automobile. A controller is in data communication with the lane sensors and programmed to determine proximity and motion status data regarding an automobile in the drive through lane. A pedestrian visual alert member is positioned proximate the pedestrian door of the restaurant and includes Stop, Go, and Caution indicator lamps. An appropriate lamp is energized by the controller depending if the lane sensors detect an automobile moving downstream in the drive-through lane, stopped at the pick-up window, or the lane is clear. The system may also include pedestrian sensors inside the restaurant and a lane visual alert member having indicator lamps to indicate a status of pedestrian traffic.
US09836956B2
A trainable transceiver for controlling a device includes an antenna configured to receive power from a power source, at least one orientation sensor, and a control circuit coupled to the antenna and the at least one orientation sensor. The control circuit is configured to determine an orientation of the antenna based on data from the at least one orientation sensor. The control circuit is further is configured to control the amount of power received by the antenna based on the determined orientation of the antenna. The trainable transceiver is configured to be capable of controlling the device based on at least one signal characteristic stored in memory and determined based on a signal received from an original transmitter.
US09836953B2
Hazard detector for providing a pre-alarm of a developing hazardous condition can include a detection module that detects a hazard level of smoke or carbon monoxide, a light source that generates light, a speaker that generates an audible sound, a horn that generates an audible alarm that a higher volume than the speaker, and a processing module. The processing module can receive the detected hazard level and compare it with the pre-alarm threshold and the emergency threshold. The processing module can determine that the hazard level is greater than the pre-alarm threshold and less than the emergency threshold and cause an audible pre-alarm speech to be generated via the speaker that warns of the developing hazardous condition.
US09836946B2
This application generally relates to systems and methods for authenticating a bulk quantity of a consumable product with a corresponding product. More specifically, the invention associates a bulk quantity of the consumable product with a product parameter such as a consumption rate of the consumable product within the corresponding product; provides and authorizes a key and/or reader with the bulk quantity and consumption rate data to a specific corresponding product wherein the bulk quantity and consumption rate data are correlated to a maximum consumption quantity value; monitoring consumption of the consumable product within the corresponding product until the maximum consumption quantity value is reached; and providing an event output to the corresponding product when the maximum consumption quantity value is realized.
US09836942B2
A person support apparatus supports a person in a laying-down or a seated position. One or more body-mounted sensors detect changes in the position of the person relative to a reference. A control system receives output from the body-mounted sensor or sensors through a remote coupling. The control system uses patient position information obtained from the body-mounted sensors to determine whether the person has experienced a change-in-position and/or a change-in-activity event. Alternatively or in addition, the position of the person situated on a person support apparatus is detected using one or more sensors that are not body-mounted, but rather are coupled to the person support apparatus or to another component of a patient support system. The patient position information is used to estimate the patient's torso angle. The estimated torso angle is used to assess the patient's condition.
US09836936B1
An object tracking system including an RFID reader having at least one antenna positioned along an entranceway of an object storage facility. A processor communicates with RFID reader and runs software to perform the steps of: (i) monitoring the phase angle of a target RFID tag; and (iii) returning an indicator of whether the target RFID tag is or is not moving based at least in part on whether the phase angle has changed.
US09836935B2
The present invention discloses a point of sale (POS) structure that is includes an Electronic Article Surveillance (EAS) system.
US09836931B1
A method may include obtaining sensor data from sensors of a primary device, determining a sensor pattern based on the sensor data, generating a response based on the sensor pattern, and sending a signal over a network to a secondary device to trigger an action of the secondary device. The signal may be based on the sensor pattern.
US09836930B2
A device for communicating a physical touch is disclosed. The device including: an array of pistons numbering greater than 25 per square inch, each piston having a contact surface; an actuator array to independently move each piston; and a controller to determine a depth position of each piston in the array of pistons, wherein each of the pistons comprises a cylinder and a pin disposed in the cylinder. The device may be used with a communication system including a high speed data transmission and sensory system to reproduce the sensation of touch by translating an actuation of the array pins. The actuation may be affected by a controlled continuous transfer of a fluid between pressure zones. Additional sensory effects including texture, softness, humidity, chemistry and temperature may be transmittable through the device.
US09836920B2
Systems and method for providing a gambling hybrid game having manual triggering of gambling events is disclosed. The systems and method involve providing a proposition of a gambling event to a user and receiving an input accepting the proposition from a user. The gambling event that is associated with the proposition is then resolved. The results of the gambling event are then determined and the wagers are resolved. The results of the gambling event are then used to change variables in a set of game variables that are applied in the game.
US09836914B2
A gaming system is disclosed which comprises a plurality of display positions disposed in a display area, a symbol selector arranged to select a plurality of symbols for display at respective display positions, and an outcome evaluator arranged to determine whether the selected symbols correspond to a winning outcome with reference to at least one of a plurality of defined win lines. Each of the defined win lines comprises at least one display position, and at least some of the win lines comprise differing numbers of display positions. A corresponding method of gaming is also disclosed.
US09836910B1
A line of intricate, home-based vending machines specially designed for housing and organizing a multitude of shoes and boots. Design intent of this product is to provide a more convenient, as well as accessible, means of storing, maintaining, and accessing footwear, particularly in residences where storage space is limited.
US09836903B2
A door lock mechanism is disclosed that includes door lock and alarm features. The mechanism includes a controller and a sensor useful to detect motions that are representative of attempted access through a door to which the door lock mechanism is attached. The controller can set an alarm condition if a measured motion, such as a measured acceleration, meet and/or exceeds a threshold. If an appropriate access control credential is provided through a user device then the alarm condition may not be set by the controller. The door lock mechanism can be coupled to a remote station via a communications link if needed, such as a radio frequency link. The remote station can additionally be in communication with the door lock mechanism via a network. The remote station can be used to send and receive messages regarding door lock mechanism status, configuration, etc.
US09836896B2
In accordance with one embodiment, an access control system is disclosed. The access control system comprises an access control panel including a touchable surface, a multi-dimensional touch sensor under the touchable surface, and a processor coupled to the multi-dimensional touch sensor. The multi-dimensional touch sensor captures a multi-dimensional motion signal including a micro-motion signal component representing neuro-mechanical micro-motions of a user touching the multi-dimensional touch sensor. The processor performs signal processing of the multi-dimensional motion signal to obtain the micro-motion signal component; and extracts unique values of predetermined features from the micro-motion signal component to form a neuro-fingerprint (NFP) that uniquely identifies the user. The NFP can be used as a gatekeeper to control entry into homes, offices, buildings, or other real properly typically protected by access control.
US09836893B2
Herein described is at least a system, method, and/or non-transitory computer-readable storage medium for computing locomotive health based on input parameters such as locomotive defect data and locomotive inspection data. Examples of locomotive health attributes for which values may be computed include an overall health attribute, a power level health attribute, a defect severity health attribute, a trail only health attribute, and a health reason attribute. Furthermore, various events may be defined that may trigger computation of the locomotive health attribute values.
US09836891B2
A shape data generation method includes: generating a target shape of transformation from plural tomographic images of an object; specifying, from among plural vertices of a first shape that is a reference shape of the object, plural first vertices, each first vertex of which satisfies a condition that a normal line of the first vertex passes through a point that is located on the target shape and is located on a boundary of the object in any one of the plural tomographic images; identifying, for each of the plural first vertices, a second vertex that internally divides a segment between the first vertex and the point; transforming the first shape so as to put each of the plural first vertices on a corresponding second vertex; setting a shape after the transforming to the first shape; and executing the first specifying and the subsequent processings a predetermined number of times.
US09836890B2
Systems and methods for image based location estimation are described. In one example embodiment, a first positioning system is used to generate a first position estimate. A set of structure façade data describing one or more structure façades associated with the first position estimate is then accessed. A first image of an environment is captured, and a portion of the image is matched to part of the structure façade data. A second position is then estimated based on a comparison of the structure façade data with the portion of the image matched to the structure façade data.
US09836886B2
There is provided a client terminal including a determination unit configured to determine whether an overhead view image is associated with a position indicated by a user, and a display control unit configured to perform control so that the overhead view image is displayed on a display unit in accordance with a determination result obtained by the determination unit.
US09836870B2
A perspective-correct communication window system and method for communicating between participants in an online meeting, where the participants are not in the same physical locations. Embodiments of the system and method provide an in-person communications experience by changing virtual viewpoint for the participants when they are viewing the online meeting. The participant sees a different perspective displayed on a monitor based on the location of the participant's eyes. Embodiments of the system and method include a capture and creation component that is used to capture visual data about each participant and create a realistic geometric proxy from the data. A scene geometry component is used to create a virtual scene geometry that mimics the arrangement of an in-person meeting. A virtual viewpoint component displays the changing virtual viewpoint to the viewer and can add perceived depth using motion parallax.
US09836858B2
A method for generating a combined projection image from a medical inspection object, includes steps of capturing a set of initial projection images; reconstructing a first and a second three-dimensional volume from the set of initial projection images; generating a first re-projection image from the first three-dimensional volume and a second re-projection image from the second three-dimensional volume; weighting the first re-projection image and the second re-projection image; and combining the weighted first re-projection image and second re-projection image for generating the combined projection image.
US09836845B2
Methods and apparatus for determining location of objects surrounding a user of a 3D rendering and display system and indicating the objects to the user while the user views a simulated environment, e.g., on a headmounted display, are described. A sensor, e.g. camera, captures images or senses the physical environment where the user of the system is located. One or more objects in the physical environment are identified, e.g., by recognizing predetermined symbols on the objects and based on stored information indicating a mapping between different symbols and objects. The location of the objects relative to the user's location in the physical environment is determined. A simulated environment, including content corresponding to a scene and visual representations of the one or more objects, is displayed. In some embodiments visual representation are displayed in the simulated environment at locations determined based on the location of the objects relative to the user.
US09836839B2
Embodiments disclosed herein are directed to systems and methods for determining a presence and an amount of an analyte in a biological sample. The systems and methods for determining the presence of an analyte utilize a plurality of images of a sample slide including multiple fields-of-view having multiple focal planes therein. The systems and methods utilize algorithms configured to color and grayscale intensity balance the plurality of images and based thereon determine if the plurality of images contain the analyte therein.
US09836834B2
A method is provided for calculating a region of interest in a second image using an initial region of interest in a first image. The first and second images are linked by a spatial transformation function. The method includes steps of (i) generating a first polygonal mesh enclosing the initial region of interest in the first image; (ii) computing a second polygonal mesh in the second image by applying the spatial transformation function to the first polygonal mesh, and (iii) identifying image elements within the second image, that belong to the area enclosed by the second polygonal mesh. Also provided are a computer program and a system.
US09836828B2
Near-to-eye displays within head mounted devices offer both users with and without visual impairments enhanced visual experiences either by improving or augmenting their visual perception. Unless the user directly views the display without intermediate optical elements then the designer must consider chromatic as well as other aberrations. Within the prior art the optical train is either complex through additional corrective elements adding to weight, cost, and size or through image processing. However, real time applications with mobile users require low latency to avoid physical side effects. Accordingly, it would be beneficial to provide near-to-eye displays mitigating these distortions and chromatic aberrations through pre-distortion based electronic processing techniques in conjunction with design optimization of the optical train with low weight, low volume, low complexity, and low cost. Further, it would be beneficial to exploit consumer grade low cost graphics processing units rather than application specific circuits.
US09836824B2
A system includes obtaining de-noised reconstructed image data and edge improving a sub-set of the de-noised reconstructed image data corresponding to edges of structure represented in the de-noise reconstructed image data. A system (100) includes an edge detector (202) that detects an edge map of edge locations within de-noised reconstructed image data, a noise image data generator (204) that generates noise image data by subtracting the reconstructed image data by the de-noised reconstructed image data, a noisy edge image data generator (206) that generates noisy edge image data by multiplying the noise image data and the edge map, and an edge improver (208) that generates edge improved de-noised image data by adding the noisy edge image data and a product of a weight and the de-noised reconstructed image data.
US09836821B2
An image quality enhancing apparatus which make a learning-type image quality enhancing method utilizing a sparse expression practical are provided. The apparatus calculates, from the feature quantity of an image, coefficients of low-image-quality base vectors expressing a feature quantity with a linear sum and generates the image with the image quality enhanced by calculating a linear sum of high-image-quality base vectors using the calculated coefficient. When calculating the coefficient, the number of base vectors with non-zero coefficients is determined, the determined number of base vectors is selected, and a solution of a coefficient matrix is calculated by assuming the coefficients of the base vectors other than the selected base vectors are zero. The amount of processes necessary for obtaining a sparse solution of a coefficient matrix can be reduced by adjusting the number of base vectors with non-zero coefficients, and a practical image quality enhancing apparatus can be realized.
US09836820B2
A method upsamples an image using a non-linear fully connected neural network to produce only global details of an upsampled image and interpolates the image to produce a smooth upsampled image. The method concatenates the global details and the smooth upsampled image into a tensor and applies a sequence of nonlinear convolutions to the tensor using a convolutional neural network to produce the upsampled image.
US09836814B2
A display control apparatus includes a receiver that receives a recognition result of a change in environment around a vehicle, and a controller that controls an image generation apparatus to generate an image corresponding to a presentation image to be displayed on the display medium. The controller generates and outputs a control signal to the image generation apparatus to control the image generation apparatus based on the recognition result so as to deform the presentation image radially on the display medium such that the deformed presentation image moves toward at least one of sides of the display medium and disappears sequentially to the outside of the display medium across edges of the display medium.
US09836807B2
A phase estimation method estimates the phase of signal components using a point spread function. The method obtains a point spread function that expresses complex frequencies at a non integer location in terms of integral frequencies, for a complex frequency of a signal at a non integer location in a complex frequency domain. It obtains complex frequencies of the signal for the integral frequencies, and computes a sum of products of the complex frequencies of the signal at the integral frequencies with the corresponding complex values of the point spread function to provide an estimate of phase of the signal at the non integer location.
US09836804B2
Ranking and displaying comparable properties entails receiving appraisal information comprising a subject property and appraiser-chosen comparable properties corresponding to the subject property. Property data corresponding to a geographical area is accessed, in support of determining model-chosen comparable properties based upon the appropriateness of each of the comparable properties as comparables for the subject property. A map image is displayed for the geographical area, along with indicators on the map image indicative of the subject property, at least one of the appraiser-chosen comparable properties, and at least one of the model-chosen comparable properties.
US09836803B2
A network system is provided. The network system includes: at least one component selected from an energy receiving unit receiving energy and an energy management unit managing the energy receiving unit. The energy receiving unit or the energy management unit receives energy rate related information; an energy usage amount or a usage rate of when the component is controlled on the basis of at least the energy rate related information is less than that of when the component is controlled without the basis of at least energy rate related information; if the energy rate related information is high cost information, a function of one component constituting the energy receiving unit is limited; and an operating time or an output of the energy receiving unit is adjusted in correspondence to the limited function of one component.
US09836800B2
In one embodiment, a system may include a processing device to incrementally unlock, for an account corresponding to a member of an electronic social networking system, member actions based on a score. One member action may be unlocked in response to the score reaching a first threshold, and another member action may be unlocked in response to the score reaching a second different threshold. A remote device that is associated with the account may be updated with one or more graphical user interfaces. Each graphical user interface may be to enable a corresponding one of the member actions of that are incrementally unlocked. Other embodiments may be disclosed or claimed.
US09836798B2
Particular embodiments of the present invention are directed to providing an application programming interface allowing developers to create a single version of a social networking application configured to execute on more than one social network, wherein such execution may be customized with respect to each particular social network in which the social networking application may execute. The same or alternative embodiments may also provide an application programming interface for saving and/or retrieving social networking application data in and/or from a common data store, allowing aggregation of data specific to the cross-network social networking application such that the data is available across multiple social networks.
US09836795B2
Systems and methods are disclosed herein for processing data in connection with insurance information submissions. The system may be configured to receive entity data relating to an entity for which insurance coverage is sought, and query an interface of a third-party platform based on the entity data. The system may then be configured to receive third-party platform interface data from the third-party platform, analyze the data to determine a web site address for a web page on the third-party platform relating to the entity, and retrieve third-party platform web site data from the web page on the third-party platform indicative of content related to the entity. The system may be configured to pre-fill insurance forms relating to the entity based on the third-party platform data.
US09836784B2
A method of delivering advertising in an online environment includes determining a context of a user operating a client computer to interact with an e-commerce website, where the determined context representing an intent of the user to locate a product for purchase, defining a relation between one or more of a plurality of advertisements and the product based on at least one of a plurality of relevance types, and displaying, to the user, at least one of the advertisements having the relation to the product.
US09836770B2
An application on a user device sends a request for promotional material to a server while the application is active on a user device. The application receives the promotional material from the server and stores the promotional material in a data store on the user device. A management client on the user device receives a user interaction with the promotional material and sends data representing the user interaction to the server independent of web-browser technology.
US09836767B2
Methods and systems to facilitate real time communications and commerce via answers presented to questions. One embodiment includes one or more web servers to receive from a second user an answer to a question of a first user, and to present the answer with a communication reference of a connection provider to a third user; a session border controller of the connection provider to interface with a packet switched network; and one or more telecommunication servers of the connection provider coupled with the session border controller to connect the third user to the second user for real time communications in response to a request made via the communication referenced. One embodiment includes: receiving from a second user an answer to a question of a first user; and presenting to a third user the answer with a reference for requesting fee-based content from or real time communications with the second user.
US09836766B1
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for personalizing landing pages. In one aspect, a method includes generating, by one or more servers belonging to a first domain and for a request, a personalized landing page that includes the personalized landing page data, wherein the landing page belongs to the first domain, and the landing page includes at least one link to a resource of the first party that belongs to the second domain; and providing, by the one or more servers, the personalized landing page to the user device, wherein the personalized landing page, when processed by the user device, generates a personalized landing page environment that belongs to the first domain.
US09836759B2
Rewards programs in which rewards are awarded for a series of transactions using a universal transaction associating identifier to associate transactions in common within each rewards program in a reward processing system. The system includes resource providers, a rewards program rule implementer having access to a rewards program database, and an implementer processor. The implementer processor receives transaction data whenever a transaction occurs using the universal transaction associating identifier, determines when a consumer has performed the transactions satisfying rules requirements, and identifies and awards a reward, including vouchers, for the consumer. The reward processing system generates a universal transaction associating identifier from a plurality of identification sources and provides for objects containing the universal transaction associating identifier. The reward processing system issues and redeems vouchers exchangeable for rewards. The system targets consumers and transmits messages adaptive to system elements, including rules requirements and the universal transaction associating identifier.
US09836758B2
A method for creating a control group for campaign measurements includes: storing a plurality of consumer profiles, each profile including data related to a consumer including an account identifier, spend behavior, and microsegment associated with the consumer; receiving a plurality of measurement profiles, each profile including data related to a consumer including a specific account identifier and indication of participation or non-participation in a campaign; associating each consumer profile with a measurement profile where the included account identifier corresponds to the specific account identifier of the measurement profile; identifying a campaign group, the campaign group including consumer profiles, each profile including a common microsegment and spend behavior and associated with a measurement profile indicating participation in the campaign; and identifying a control group, the control group including consumer profiles, each profile including the common microsegment and spend behavior and associated with a measurement profile indicating non-participation in the campaign.
US09836756B2
Various systems and methods for tracking and analyzing emotional engagement of people while shopping are described herein. A system for tracking and analyzing emotional engagement of people while shopping includes an image processing module to: access image data from an electronic data storage, the image data including a person in a retail environment; and detect the person in the image data; an emotion detection module to determine an emotion expressed by the person; an object detection module to determine an object with which the person is interacting; and a marketing module to: select a sales action based on the emotion and the object; and execute the sales action.
US09836753B2
A computing system for encouraging the performance of a task comprises association data, a proxy module, a display module, and a reward module. The association data associates tags with stimuli related to performing tasks. The proxy module is configured to receive encoded data, to identify tags in the encoded data that have associated stimuli in the association data, and to generate modified encoded data that includes data representative of at least one of the stimuli. The display module is configured to receive the modified encoded data, to display information based at least in part on the modified encoded data, and to provide at least one mechanism for a user to perform a task related to at least one of the stimuli. The reward module is configured to reward a user for performing tasks related to the stimuli.
US09836740B1
A method and apparatus for an RFID tag device that uses dynamic identifiers for transactions rather than a fixed identifier. An associated device communicates with the RFID tag device and obtains dynamic identifiers for transactions and provides the dynamic identifiers to the RFID tag device. The RFID tag device is protocol-agile and can be configured to operate using different protocols to complete transactions.
US09836738B2
A payment card transaction clearing system includes a payment card network. A file distribution system coupled to the payment card network includes a split processor configured to receive a batch of payment card transaction records from the payment card network, and split the batch of payment card transactions into one or more split files according to one or more processing agreements. A split monitor processor is configured to send the one or more split files to the payment card network.
US09836735B2
The invention relates to a method for performing authenticated bank card payment transaction, comprising registering a user (12) having a communication device (10) suitable for data communication through a communication channel (25) and comprising data storage (14) and data input interface (26). The method comprises the steps of: providing the user (12) with a transaction initiating program (16) executable on the communication device (10), assigning to the user (12): a user pin code (12b) and a unique identifier (18) of the user (12); allowing the user (12) via the program (16) to input transaction data (40), bank card data (22), the user pin code (12b) and the unique identifier (18), allowing the user (12) via the program (16) to generate and transmit through a communication channel (25) a transaction data package (50) comprising the transaction data (40), bank card data (22), the user pin code (12b) and the unique identifier (18), receiving the transmitted data package (40) and opening it, authenticating the user (12) on the basis of the unique identifier (18) and the pin code (12b), and transmitting the transaction data (40) and the bank card data (22) to a transaction performing unit (34).
US09836734B2
Systems and methods are disclosed herein for providing an electronic receipt for a vending machine transaction. Upon conclusion of a vending machine transaction a screen on the vending machine displays an optically encoded electronic receipt. The optically encoded electronic receipt may encode a transaction identifier and may additionally encode details of the transaction. The vending machine may also transmit transaction data to a server. A user computing device may scan the optically encoded electronic receipt and retrieve a transaction identifier. Using the transaction identifier, the user computing device may request transaction data from the server either directly or by way of a server owned or controlled by a different entity. Additional content, such as advertisements may be transmitted with or for display with transaction data.
US09836727B1
The disclosed embodiments include systems and methods for executing a point of sale deposit. In one embodiment, a system may include one or more memory devices storing software instructions, and one or more processors configured to execute the software instructions to receive transaction information related to a point of sale deposit from a client device, and generate a pending deposit transaction based on the transaction information. The one or more processors may be further configured to execute the software instructions to receive a first transaction token from the client device, receive a second transaction token from a third-party device, match the first transaction token to the second transaction token, and complete the pending deposit transaction based on the match.
US09836726B2
A system and a method for conducting credit card transactions through a mobile device of a user. The mobile device comprises an image acquisition unit and a mobile application operated by the mobile device. The system enables acquiring an image of a client's credit card, using the image acquisition unit; analyzing data of the image; outputting details of the credit card from the analysis; verifying the output details, wherein the verification is further carried out through the mobile application; verifying authorization of inputted monetary transaction, wherein the mobile application enables verifying the authorization by communicating with the billing center, associated with at least one credit company associated with the credit card over at least one communication network, wherein the communication is carried out by the mobile application using the mobile device; and conducting monetary transactions using the verified credit card details.
US09836725B2
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for determining travel information. One of the methods includes obtaining flight information for each of a plurality of users, the flight having a flight identifier and associated with a particular scheduled departure time and departure location; based on the scheduled departure time, obtaining location information for user devices associated with each user of the plurality of users; determining that the respective user devices associated with a first group of users of the plurality of users, has a location associated with the departure location; determining that the respective mobile devices associated with users of the first group are no longer in communication a mobile network; and using the respective times at which the user devices are determined to no longer be in communication with the mobile network along with the scheduled departure time to determine a departure time.
US09836724B2
Email viewing techniques are described. In implementations, a determination is made regarding one or more types of content that are included in an email through examination of metadata that describes the one or more types of content. The determination is made responsive to selection of an email in a user interface for output. A choice is made from one of a plurality of views for the email based on the determination; and the email is output in a user interface using the chosen view.
US09836718B2
Systems and methods of processing items. Items in a distribution network or process may be scanned at every handling point in the distribution network, and each scan is recorded in a central repository. The scan information can be used to generate real-time access to data, analytical tools, predictive tools, and tracking reports.
US09836714B2
Systems, methods and computer program products for determining costs of vehicle repairs and times to major repairs. In one embodiment, a system includes a computer processor, a data storage device, and an output device. The processor receives information from a user identifying a vehicle of interest. The processor retrieves repair data items that have characteristics common to the vehicle of interest from a database stored in the data storage device. The processor determines repairs that are expected to be necessary for the vehicle of interest based on the retrieved repair data items, and determines the costs associated with the identified expected repairs. The processor provides output to the user indicating the repair costs and/or the times at which the repairs are likely to be necessary. The output may be in graphical and/or numerical form.
US09836708B2
Systems and methods of dynamically identifying supported items in an application are described. In one example, an analytics engine receives an indication of available client data, a user's enterprise role, and/or a user's security level. The analytics engine identifies a first subset of supported semantic items (e.g., business topics, business topics, measures, etc.) and a second subset of unsupported semantic items. For example, a semantic item may be supported if corresponding client data is available for analysis and the user's role/security level enable access to the client data. The analytics engine may send data including the supported semantic items and excluding the unsupported semantic items to an application.
US09836705B2
A vehicle system includes a navigation system, a communication interface, and a processing device. The navigation system determines a first vehicle location. The communication interface receives social network information over a communication network. The social network information includes a second vehicle location. A processing device determines the proximity of the first vehicle location to the second vehicle location and generates a message based on the proximity.
US09836698B2
Methods and systems transform a given single-qubit quantum circuit expressed in a first quantum-gate basis into a quantum-circuit expressed in a second, discrete, quantum-gate basis. The discrete quantum-gate basis comprises standard, implementable quantum gates. The given single-qubit quantum circuit is expressed as a normal representation. The normal representation is generally compressed, in length, with respect to equivalent non-normalized representations. The method and systems additionally can map normal representations to canonical-form representations, which are generally further compressed, in length, with respect to normal representations.
US09836691B1
A computer-implemented method that includes receiving, by a processing unit, an instruction that specifies data values for performing a tensor computation. In response to receiving the instruction, the method may include, performing, by the processing unit, the tensor computation by executing a loop nest comprising a plurality of loops, wherein a structure of the loop nest is defined based on one or more of the data values of the instruction. The tensor computation can be at least a portion of a computation of a neural network layer. The data values specified by the instruction may comprise a value that specifies a type of the neural network layer, and the structure of the loop nest can be defined at least in part by the type of the neural network layer.
US09836687B1
A transaction card includes a card body that may comprise a card body comprising a ceramic material, the card body including a primary surface and a first mating surface. A card backer comprises a metallic material and includes a secondary surface and a second mating surface. A portion of the first mating surface and a portion of the second mating surface are coupled together.
US09836683B2
An electronic device including an electronic assembly and an enclosure. The electronics assembly including a host interface and a direct user input interface. The direct user input interface remains exposed when the device is connected to a host via the host interface. The enclosure, substantially in the form factor of a microSD device, forms the outer boundary of the electronic device, overmolded on the electronics assembly.
US09836679B2
A scanner camera is presented with a controller that selectively illuminates white and/or colored light sources, during each particular color illumination of an object being imaged, the camera captures a monochrome image of that particular color illuminated object. One or more of the images are processed by the controller to obtain information about the object being imaged.
US09836666B2
Embodiments are provided to search for a dictionary image corresponding to a target image. The method includes detecting keypoints in a set of dictionary images. The set of dictionary images includes at least one dictionary image having a plurality of pixels. At least one random pair of pixels is selected among the detected keypoints of the dictionary image on the basis of candidate coordinates for pixels distributed around the detected keypoints of the dictionary image. A feature vector of each keypoint of the dictionary image is calculated, including calculating a difference in brightness between the selected pairs of pixels of the dictionary image. The calculated difference in brightness is an element of the feature vector. Keypoints of a target image are detected.
US09836665B2
In order to reduce the labor and processing load required during list production and list verification without requiring a specialized reading apparatus, and achieve sufficient identification performance, this management system includes a list storage means that stores a list of objects to be managed, an identification image generating means that detects, from an input image, an identifying part of the objects to be managed and generates the identification image in which the identifying part detected is depicted at a predetermined orientation and size in an image region, an identification image recording means that, when a first image capturing the identifying part of an object to be managed is inputted, records an identification image generated from the first image in the list of objects to be managed as the identification image of a designated identification unit and an identification image verification means that, when a second image capturing the identifying part of an object to be managed is inputted, uses an identification image generated from the second image as a key image, and verifies the key image against respective identification images recorded in the list of objects to be managed.
US09836656B2
A device is provided for the expanded representation of a surrounding region of a vehicle, the device having an imaging component for the visual representation of the surrounding region. Information from a road model is additionally able to be superimposed on the visual representation of the surrounding region.
US09836655B2
An information processing apparatus including a memory storing instructions, and at least one processor configured to process the instructions to obtain an orientation, size, and position of a first subject in a first image, and an orientation, size, and position of a second subject in a second image, generate an estimated position of the first subject in the second image based on the orientation, size, and position of the first subject in the first image and the orientation and size of the second subject in the second image, calculate a distance between the estimated position of the first subject in the second image and the position of the second subject in the second image; and determine whether or not the first subject is the second subject based on the distance.
US09836652B2
A mechanism is provided for indicating an area of an object that is considered dangerous to a user via a head mounted display (HMD) system. The object being used by the user and one or more areas of the object that are considered dangerous are identified. Responsive to identifying one or more areas of the object that are considered dangerous, an overlay for each of the one or more areas of the object that are considered dangerous is generated. The overlay for each one or more areas of the object that are considered dangerous is displayed via a display layer of the HMD system so that the one or more areas of the object that are considered dangerous are identified as an overlay to the object that is being seen by the user through the HMD system.
US09836647B2
An iris biometric recognition module includes technology for capturing images of an iris of an eye of a person, whether the person is moving or stationary, and whether the person is located near the iris image capture device or at a distance from the iris image capture device. The iris biometric recognition technology can perform an iris matching procedure for, e.g., authentication or identity verification purposes. The iris biometric recognition module can be incorporated into, for example, a door lock assembly and other access controlled devices, mechanisms, and systems.
US09836642B1
Approaches are described which enable a computing device (e.g., mobile phone, tablet computer) to utilize one or more facial recognition techniques to control access to the device and to detect when artificial representations of a user, such as a picture or photograph, are being used in an attempt to gain access to the device. Evidence indicative of artificial representations may include lack of changes in facial skin color between multiple images captured by a camera, ability to track one or more features of the human face while the camera is rotated or moved, presence of secular reflections caused by an illumination device, absence of shadows in the image, and others.
US09836641B2
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating numeric embeddings of images. One of the methods includes obtaining training images; generating a plurality of triplets of training images; and training a neural network on each of the triplets to determine trained values of a plurality of parameters of the neural network, wherein training the neural network comprises, for each of the triplets: processing the anchor image in the triplet using the neural network to generate a numeric embedding of the anchor image; processing the positive image in the triplet using the neural network to generate a numeric embedding of the positive image; processing the negative image in the triplet using the neural network to generate a numeric embedding of the negative image; computing a triplet loss; and adjusting the current values of the parameters of the neural network using the triplet loss.
US09836628B1
In an approach for identifying an object using an electromagnetic tag, an electromagnetic signal is received by a sensor, wherein the electromagnetic signal originates from an electromagnetic tag affixed to an object, and wherein the electromagnetic signal passes through a physical propagation channel. A processor searches a database for an electromagnetic signature corresponding to the electromagnetic signal, wherein the database comprises, at least, object information associated with the electromagnetic signature. A processor determines the electromagnetic signal corresponds to the electromagnetic signature. A processor presents the object information associated with the electromagnetic signature.
US09836621B2
One or more systems and/or methods for storing personal information within a first device and/or for providing personal information from the first device to the second device are provided. The first device (e.g., a smartphone) may identify a user interface (e.g., a movie streaming website) populated with user specified data (e.g., a password). The user specified data may be evaluated to identify personal information of the user (e.g., a movie streaming website password). The personal information may be stored within the first device. Responsive to determining that a second device (e.g., a smart television) displays a personal information input field (e.g., a movie streaming website password input field), an input event comprising the personal information may be provided from the first device to the second device. The input event may invoke the second device to input the movie streaming website password into the movie streaming website password input field.
US09836613B2
Methods and apparatuses are presented for obfuscating the locations of terrestrial wireless transceivers, including wireless access points and femtocells. According to some embodiments, a method may receive, by a mobile device, data for a terrestrial wireless transceiver, wherein the data includes location coordinates of the terrestrial wireless transceiver, and wherein the location coordinates include an error term. Additionally, the method may include determining the error term based on the data. Furthermore, the method may include determining a corrected location of the terrestrial wireless transceiver by removing the error term from the location coordinates. In some instances, the data can further include a unique identifier associated with the terrestrial wireless transceiver, and wherein the error term is further determined based on the unique identifier.
US09836610B2
An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a change in virtual memory mapping. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.
US09836600B2
A multi-stage event detector for monitoring a system, the multi-stage event detector including: a process generator operable to generate main and sub-processes, each main and sub-process being operable to generate and initiate a detection agent each of which is operable to be triggered by detecting the occurrence of a trigger event and to report back to its generating process or sub-process upon being so triggered. Each process or sub-process is operable to respond to receipt of a report from a triggered detection agent by reporting the detection of a multi-stage event to an overall controller.
US09836597B2
Systems and methods prevent or restrict the mining of content on a mobile device. For example, a method may include identifying a mining-restriction mark in low order bits or high order bits in a frame buffer of a mobile device and determining whether the mining-restriction mark prevents mining of content. Mining includes non-transient storage of a copy or derivations of data in the frame buffer. The method may also include preventing the mining of data in the frame buffer when the mining-restriction mark prevents mining.
US09836592B2
Example implementations relate to fingerprint scans with power buttons. For example, a computing device may include a power button and a processor. The power button receives a user input associated with an activation of the power button to turn on the computing device and scans a fingerprint associated with the user input while the computing device is initialized in response to the activation. The processor determines whether the fingerprint matches an authorized fingerprint from a database of stored fingerprints, identifies an account associated with the fingerprint when the fingerprint matches the authorized fingerprint, and provides a desktop environment associated with the account.
US09836583B2
An automated medication adherence system. The automated medication adherence system may comprise: a housing, an electronic interface, a plurality of reservoirs, one or more sensors, and at least one pill delivery and lock-out module. The electronic interface is programmable to accept data relating to a medication, including at least one of a pill identify, a user identity, a dosage schedule, and a side effect. The electronic interface actuates rotation of a reservoir, which is configured to receive, store, and dispense pills, tablets, and capsules of various sizes accurately and precisely. The sensors monitor medication input and output, and alerts a user when medication has been dispensed and needs to be taken.
US09836582B2
A data processing system configured for computer visualization of drugs for drug interaction information retrieval is disclosed. For each of multiple different substances and using a camera within the mobile or other computing device, imagery of at least one external characteristic of a physical body of the substance is acquired. An identity of each of the multiple different substances is determined based upon the at least one external characteristic from the acquired imagery. Drug interaction data is retrieved for each of the multiple different substances using the determined identities. Drug interaction data for at least one of the multiple different substances is correlated with at least one other of the multiple different substances. At least one generic substance and/or cost information of at least one of the multiple different substances is identified. The correlated drug interaction data, the at least one generic substance, and/or the cost information are displayed.
US09836581B2
One method for supporting a patient through a treatment regimen includes: accessing a log of use of a native communication application executing on a mobile computing device by a patient; selecting a subgroup of a patient population based on the log of use of the native communication application and a communication behavior common to the subgroup; retrieving a regimen adherence model associated with the subgroup, the regimen adherence model defining a correlation between treatment regimen adherence and communication behavior for patients within the subgroup; predicting patient adherence to the treatment regimen based on the log of use of the native communication application and the regimen adherence model; and presenting a treatment-related notification based on the patient adherence through the mobile computing device.
US09836580B2
Various systems and methods are provided that graphically allow health insurance company personnel to identify patient diagnoses that are not accounted for by the health insurance company. Furthermore, the various systems and methods graphically allow health insurance company personnel to identify patients that have not submitted claims for documented ailments or conditions. Thus, the health insurance company may be able to improve its chances of receiving transfer payments from other health insurance companies and/or receiving higher star ratings.
US09836571B2
A method may include: specifying a random nets credit (RNC) statistic for nets subject to random noise in a static timing analysis of an initial integrated circuit (IC) design; calculating an upper bound for a delta delay of each net using the RNC statistic; identifying each net with a delta delay that exceeds the upper bound; identifying all nets including fan-in and fan-out cones connected to each net that exceeds the upper bound and performing a higher accuracy timing analysis for all nets that are marked. Using the upper bound for each delta delay of the nets subject to ransom noise, the delta delay of each net subject to a non-random noise, and the delta delay for all identified nets, to adjust the initial IC design, to close timing and generate a final IC design.
US09836558B2
A system for testing an electrical circuit includes a handheld device, and first and second plug-in modules. The handheld device includes a first sensor that senses a current within the electrical circuit, and a second sensor that senses a voltage within the electrical circuit. The first plug-in device is connectable to a first outlet of the electrical circuit and configured to provide an identification number on the electrical circuit. The second plug-in device is connectable to a second outlet of the electrical circuit and configured to display the identification number of the first plug-in device. The handheld device receives the identification number from the first plug-in device and displays the identification number.
US09836552B2
A method of visualizing and interacting with a given term graph for a given group G defined by a set of values d for a set of dimensions D and topic X, may comprise obtaining the term graph associated with the given group G and the topic X; displaying the topic X in a tag cloud; representing each term from the term graph as a tag in the tag cloud, wherein a distance of a given tag from the displayed topic X in the tag cloud represents a distance of a term represented by the given tag from the topic X in the term graph; and visually representing a tag's importance relative to one or more of resources associated with the given group G in the tag cloud.
US09836536B2
Systems and methods for facilitating collaboration between video creators/publishers and users in need of video creations and/or publication of videos are provided. A profile component receives and stores profile information regarding video creators. A video request component receives a request for at least creation of a video, the request indicating one or more characteristics associated with the creation of the video. A search component responds to the request and searches the profile information in connection with identifying one or more of the video creators that can create the video based on a correlation between their respective profile information and the one or more characteristics associated with the video creation.
US09836524B2
Certain implementations of the disclosed technology include systems and methods for internal co-convergence using clustering when there is hierarchy in the data structure. A method is included for clustering hierarchical database records into a first set of clusters having corresponding first cluster identifications (IDs), each hierarchical database record including one or more field values, the clustering based at least in part on determining similarity among corresponding field values of the hierarchical database records. The method includes receiving parent-child hierarchical relationship information for the hierarchical database records, re-clustering at least a portion of the hierarchical database records into a second set of clusters having corresponding second cluster IDs, the re-clustering based at least in part on the received parent-child hierarchical relationship information, and outputting hierarchical database record information, based at least in part on the re-clustering.
US09836519B2
Methods, computer systems, and stored instructions are described herein for densely grouping dimensional data and/or aggregating data using a data structure, such as one that is constructed based on dimensional data. When smaller tables are joined with a larger table, a server may analyze the smaller tables first to determine actual value combinations that occur in the smaller tables, and these actual value combinations are used to more efficiently process the larger table. A dense data structure may be generated by processing dimensional data before processing data from fact table. The dense data structure may be generated by compressing ranges of values that are possible in dimensions into a range of values that actually occurs in the dimensions. The compressed range of values may be represented by dense set identifiers rather than the actual compressed range of values.
US09836515B1
A computer-implemented method for adding active volumes to existing replication configurations may include (1) identifying a new volume to be added to an existing replication configuration that replicates a plurality of volumes to a remote storage device, (2) using interchangeable bitmaps to perform an initial synchronization of the new volume with the remote storage device before replicating the new volume to the remote storage device as part of the existing replication configuration, (3) determining that a replication log associated with the replication configuration is capable of flagging future writes by the application to the new volume without overflowing, and, upon making that determination, (4) replicating the new volume to the remote storage device as part of the existing replication configuration. Various other methods, systems, and computer-readable media are also disclosed.
US09836514B2
Technologies are generally described for cache based key-value store mapping and replication. In some examples, key-value stores may be mapped for data structure replication through extraction of file breaks in an existing key-value store by iterating through the store and examining changes in cache addresses to detect jumps in address values. Specially formulated queries may be executed to return the values within an address range that spans a physical storage volume in order to recover full key-value sets that are physically grouped at a current data center including record duplicates. Such sets may be used to replicate or inform the key-value sets at a new location or in a new key-value store allowing construction of a replicated database tree structure complete with record duplications that develop as tables are optimized over time.
US09836507B2
A method for dynamically building a column store database from a row store database. The method includes establishing the row store database for storing data, wherein each row includes a plurality of attributes, and wherein data in row store database is current to a temporal point in time. The method includes establishing the column store database including data structured to satisfy received analytic queries. The method includes beginning from an initial state of the column store database, for each subsequently received analytic query, importing a targeted amount of data from a corresponding temporal state of the row store database into the column store database to satisfy the corresponding subsequently received analytic query.
US09836504B2
A data processing system performs query progress estimation based on processed value packets. In the illustrative data processing system, a database query processor comprises a query optimizer that creates a query plan, and a database plan executor that executes the query plan and observes intermediate result streams processed as the query plan is executed. A value packet manager anticipates value packets during query optimization, creates value packets as the intermediate result streams are processed, and compares anticipated value packets with created value packets to determine accuracy of the anticipated value packets and estimate query progress.