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CN101052887A 可测试集成电路 失效 - 权利终止 转让

可测试集成电路
摘要：
一种集成电路(1)，包括具有时钟输出的内部时钟电路(12)，用于为集成电路(1)的功能电路(10)提供时钟。所述集成电路配置有在测试期间使用的计数器电路(16)和状态保持电路(18)。将所述集成电路切换到测试模式，并且发送测试时间间隔开始的信号。从所述测试时间间隔开始的时候，对来自内部时钟电路12的时钟脉冲进行计数，并且如果所述内部时钟电路从所述测试时间间隔开始后已经产生多于预定数目的时钟脉冲，则将状态保持电路(18)锁定至预定状态。从集成电路(1)读出与在所述测试时间间隔中状态保持电路(18)是否已经达到所述预定状态有关的信息，而且测试估计装置(2)使用所述信息来接受或拒绝集成电路(1)。
摘要（英）：

An integrated circuit (1) that comprises an internal clock circuit (12) with a clock output for clocking functional circuits (10) of the integrated circuit (1). The integrated circuit is provided with a counter circuit (16) and a state holding circuit (18) for use during testing. The integrated circuit is switched to a test mode and a start of a test time interval is signalled. Clock pulses from the internal clock circuit 12 are counted from the start of the test time interval and the state holding circuit (18) is locked into a predetermined state if the internal clock circuit has produced more than a predetermined number of clock pulses from the start of the test time interval. Information about whether the state holding circuit (18) has reached the predetermined state in the test time interval is read from the integrated circuit (1) and the information is used by a test evaluation apparatus (2) to accept or reject the integrated circuit (1).

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