A method for accessing a memory sequentially. The memory has (m+1) bit lines and at least one row of transistors, wherein m is a positive integer. This method includes the following steps. First, voltage levels of first and second terminals of the transistors are equalized to a ground voltage in a pre-discharge period. Next, the voltage levels of the first and second terminals of the ntransistor are respectively transformed into a source voltage and a drain voltage in an nreading period, and the voltage level of the second terminal of the (n+1)transistor is transformed into an isolation voltage, wherein n is a positive integer smaller than m. Thereafter, the voltage levels of the first and second terminals of the mtransistor are respectively transformed into the sourcevoltage and the drain voltage in an mreading period. The source voltage equals the ground voltage.