A display panel drive circuit includes a plurality of circuit blocks g each having a first-stage circuit and a second-stage circuit arranged in the row direction so that a signal transmission is performed between the first-stage circuit and the second-stage circuit belonging to the same circuit block. In each of the circuit blocks, the first-stage circuit and the second-stage circuit are arranged in the column direction. Inter-block common wiring Q is arranged for each two circuit blocks so that the signal transmission in one (g1) of the two circuit blocks and the signal transmission in the other (g2) of the two circuit blocks are performed at different timings by using the inter-block common wire (Q1). This can reduce the circuit area of the display panel drive circuit (driver) without requiring an external memory or a calculation circuit.