The invention relates to a manufacturing process of a silicon substrate for a power semiconductor device and is characterized in that grooves are etched on the backside of the original single-wafer N-substrate A; wherein, the depth of the grooves is half of the N+ junction depth which needs to be diffused; the width and the space of the grooves are tallied with the N+ junction depth which needs to be diffused; due to the grooves, diffusion is implemented on the backside to reach the purpose that the time for the N+ junction depth to design the N+ layer with required thickness can be reduced by half compared with the time required in the case of no groove; correspondingly, the thickness of the N+ layer formed on the front face can be thinned by half, so as to correspondingly shorten the time of diffusing and generating the N+ layer, save the time of removing the front face processing of the N+ layer and reduce the thickness of the original single wafer; besides, the invention has short production cycle and less material consumption, so as to reduce the production costs and materials costs and increase the productivity.