The invention provides a real-time simulation verification system and a real-time simulation verification method for the design of an integrated circuit of a communication system, which are used for the verification of the design of the integrated circuit of the communication system. The system and the method can be used for real-time verification of the front end and the rear end in the design of the integrated circuit of the communication system. The system and the method comprise that: a test module generates excitation data with the frame format required by a tested system by calling a related task, collects response regenerated by the tested system, compares the response value and the reference value in a verification module, and obtains a verification conclusion, and the two modules are communicated with each other in the mode of text. The system and the method can be transplanted into different system verifications as required aiming at communication systems with fixed frame format, and simultaneously the system changes the execution sequence of basic steps of verification, can be operated in real time, and reduces the time required by simulation verification. Moreover, the system not only can be applied to the simulation verification of a simple system provided with a standard serial port but also can be applied to the simulation verification of a large-scale complex communication system of a navigation receiver.