The invention provides an ultrahigh-speed comparator with low offset, and belongs to the technical field of composite signal integrated circuits. The comparator comprises a preamplification circuit, adynamic latch circuit and an output latch circuit which hare connected in sequence, wherein, the preamplification circuit comprises a fully differential input structure with a positive resistor and anegative resistor serially connected as load and is used for amplifying difference value between input signals and reference signals; the dynamic latch circuit is equipped with a bistable structure which is connected from head to tail by an inverter, and used for amplifying the output signals of the preamplification circuit and establishing preceding stage output to digital logic output level; and the output latch circuit is composed of two cross-coupled NMOS transistors and PMOS common source amplification input, and used for outputting preceding stage output in a latch time, and keeping output result of the dynamic latch circuit at high impedance state in a reset stage so as to reduce input offset voltage of the comparator, increase speed of the comparator and well meet requirements ofhigh-speed analog-to-digital converter design.