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发明公开
CN101714869A 相倍增器 有权

相倍增器
摘要：
一种相倍增器驱动器电路包括用于接收输入PWM驱动信号的第一输入。第一控制逻辑响应于该输入PWM驱动信号产生第一输出PWM驱动信号和第二输出PWM驱动信号。在第一工作模式下，输入PWM驱动信号的交变脉冲分别作为第一输出PWM驱动信号和第二PWM输出驱动信号输出。在第二工作模式下，当与第二输出PWM驱动信号相关联的第二相电流超过与第一输出PWM驱动信号相关联的第一相电流时，输入PWM驱动信号被提供作为第一输出PWM驱动信号，而当与第一输出PWM信号相关联的相电流超过与第二输出PWM信号相关联的相电流时，输入PWM驱动信号被提供作为第二输出PWM驱动信号。第二控制逻辑响应于与第一相电流相关联的第一电流与平均电流之差向第一输出PWM驱动信号的下降沿添加偏移，且响应于与第二相电流相关联的第二电流与平均电流之差向第二输出PWM信号的下降沿添加该偏移，其中平均电流包括第一电流与第二电流的平均值。驱动电路系统响应于第一输出PWM驱动信号和第二输出PWM驱动信号中的每一个生成驱动信号。
摘要（英）：

A phase doubler driver circuit includes a first input for receiving a input PWM drive signal. First control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to the input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal. Second control logic adds an offset to a falling edge of the first output PWM drive signal responsive to adifference between a first current associated with the first phase current and an average current and for adding the offset to a falling edge of the second output PWM signal responsive to a difference between a second current associated with the second phase current and the average current, wherein the average current comprises the average of the first current and the second current. Drive circuitry generates drive signals responsive to each of the first output PWM drive signal and the second output PWM drive signal.

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