The invention belongs to the technical field of an electron, particularly relates to an automated fault traversal testing method for an interconnection resource of a programmable logic device. The invention provides a method for automatically generating a test configuration set, which is irrelevant to the application; the weights of all sides are set according to the trend of a net by establishing a wiring resource map; and the configuration set is generated automatically by utilizing an improved Kruskal algorithm. For different interconnection structures of FPGA, the method achieves 100% coverage rate for the open circuit and short circuit fault in the interconnection resource, and has a few numbers of testing configurations, fast running speed and no dependency on a specified hardware structure.